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drm/amd/display: fix seamless odm transitions

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commit 75c2b7ed08 upstream.

Add missing programming and function pointers

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dmytro Laktyushkin
2023-04-18 10:11:56 -04:00
committed by Greg Kroah-Hartman
parent c41963e50a
commit 31fb25ecbb
3 changed files with 13 additions and 1 deletions
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11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@@ -1678,6 +1678,17 @@ static void dcn20_program_pipe(
if (hws->funcs.setup_vupdate_interrupt) if (hws->funcs.setup_vupdate_interrupt)
hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
unsigned int k1_div, k2_div;
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
dc->res_pool->dccg->funcs->set_pixel_rate_div(
dc->res_pool->dccg,
pipe_ctx->stream_res.tg->inst,
k1_div, k2_div);
}
} }
if (pipe_ctx->update_flags.bits.odm) if (pipe_ctx->update_flags.bits.odm)

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
View File

@@ -98,7 +98,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
optc1->opp_count = opp_cnt; optc1->opp_count = opp_cnt;
} }
static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
{ {
struct optc *optc1 = DCN10TG_FROM_TG(optc); struct optc *optc1 = DCN10TG_FROM_TG(optc);

1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
View File

@@ -250,5 +250,6 @@
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
void dcn32_timing_generator_init(struct optc *optc1); void dcn32_timing_generator_init(struct optc *optc1);
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
#endif /* __DC_OPTC_DCN32_H__ */ #endif /* __DC_OPTC_DCN32_H__ */