diff --git a/MAINTAINERS b/MAINTAINERS
index 79178dcd8ab8..14be48e1a57a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14496,3 +14496,7 @@ AMLOGIC G12B clock
 M: Qiufang Dai <qiufang.dai@amlogic.com>
 F: drivers/amlogic/clk/g12b/*
 
+AMLOGIC LCD Driver
+M:	Evoke Zhang <evoke.zhang@amlogic.com>
+F:	arch/arm64/boot/dts/amlogic/mesong12b_skt-panel.dtsi
+
diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
index 066e84953a75..d26abd6058bd 100644
--- a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
@@ -19,6 +19,7 @@
 
 #include "partition_mbox_normal.dtsi"
 #include "mesong12b.dtsi"
+#include "mesong12b_skt-panel.dtsi"
 
 / {
 	model = "Amlogic";
diff --git a/arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
index 5cea074fc9bd..f52ce3b38049 100644
--- a/arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
@@ -1,5 +1,5 @@
 /*
- * arch/arm64/boot/dts/amlogic/mesongxm_q200-panel.dtsi
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
  *
  * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
  *
@@ -32,8 +32,8 @@
 			"dsi_meas",
 			"encl_top_gate",
 			"encl_int_gate";
-		reg = <0x0 0xffd07000 0x0 0x400
-			   0x0 0xff644000 0x0 0x2000>;
+		reg = <0x0 0xffd07000 0x0 0x400     /* dsi_host */
+			0x0 0xff644000 0x0 0x2000>; /* dsi_phy */
 		pinctrl_version = <2>; /* for uboot */
 
 		/* power type:
@@ -1437,15 +1437,17 @@
 		pinctrl-names = "pwm_on";
 		pinctrl-0 = <&pwm_f_pins2>;
 		pinctrl_version = <2>; /* for uboot */
+		bl_pwm_config = <&bl_pwm_conf>;
+		bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+			&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+		bl_gpio_names = "GPIOH_4","GPIOH_5";
+
 		/* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
 		/* power index:(point gpios_index, 0xff=invalid)
 		 * power value:(0=output low, 1=output high, 2=input)
 		 * power delay:(unit in ms)
 		 */
-		bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
-			&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
-		bl_gpio_names = "GPIOH_4","GPIOH_5";
-		bl_pwm_config = <&bl_pwm_conf>;
+
 		backlight_0{
 			index = <0>;
 			bl_name = "backlight_pwm";
diff --git a/arch/arm64/boot/dts/amlogic/mesong12b_skt-panel.dtsi b/arch/arm64/boot/dts/amlogic/mesong12b_skt-panel.dtsi
new file mode 100644
index 000000000000..d1cc7dfe388c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/mesong12b_skt-panel.dtsi
@@ -0,0 +1,873 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12b_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+	lcd{
+		compatible = "amlogic, lcd-g12b";
+		dev_name = "lcd";
+		mode = "tablet";
+		status = "okay";
+		key_valid = <0>;
+		clocks = <&clkc CLKID_MIPI_DSI_HOST
+			&clkc CLKID_MIPI_DSI_PHY
+			&clkc CLKID_DSI_MEAS_COMP
+			&clkc CLKID_VCLK2_ENCL
+			&clkc CLKID_VCLK2_VENCL>;
+		clock-names = "dsi_host_gate",
+			"dsi_phy_gate",
+			"dsi_meas",
+			"encl_top_gate",
+			"encl_int_gate";
+		reg = <0x0 0xffd07000 0x0 0x400     /* dsi_host */
+			0x0 0xff644000 0x0 0x2000>; /* dsi_phy */
+		pinctrl_version = <2>; /* for uboot */
+
+		/* power type:
+		 *    (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+		 * power index:
+		 *    (point gpios_index, or extern_index,0xff=invalid)
+		 * power value:(0=output low, 1=output high, 2=input)
+		 * power delay:(unit in ms)
+		 */
+		lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+				&gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+		lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+		lcd_0{
+			model_name = "B080XAN01";
+			interface = "mipi";
+			basic_setting = <768 1024 /*h_active, v_active*/
+				948 1140 /*h_period, v_period*/
+				8 /*lcd_bits*/
+				119 159>; /*screen_widht, screen_height*/
+			lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+				50 30 0>; /*vs_width, vs_bp, vs_pol*/
+			clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+				0 /*clk_ss_level */
+				1 /*clk_auto_generate*/
+				64843200>; /*pixel_clk(unit in Hz)*/
+			mipi_attr = <4 /*lane_num*/
+				550 /*bit_rate_max(MHz)*/
+				0 /*factor(*100, default 0 for auto)*/
+				1 /*operation_mode_init(0=video, 1=command)*/
+				0 /*operation_mode_display(0=video, 1=command)*/
+				2 /*
+				   *video_mode_type
+				   *(0=sync_pulse,1=sync_event,2=burst)
+				   */
+				1 /*clk_always_hs(0=disable,1=enable)*/
+				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+			/* dsi_init: data_type, num, data... */
+			dsi_init_on = <0x05 1 0x11
+					0xff 20     /*delay(ms)*/
+					0x05 1 0x29
+					0xff 20     /*delay(ms)*/
+					0xff 0xff>; /*ending*/
+			dsi_init_off = <0x05 1 0x28
+					0xff 10     /*delay(ms)*/
+					0x05 1 0x10
+					0xff 10     /*delay(ms)*/
+					0xff 0xff>; /*ending*/
+			extern_init = <0xff>; /*0xff for invalid*/
+
+			/* power step: type, index, value, delay(ms) */
+			power_on_step = <
+				0 1 0 100
+				0 0 0 10
+				0 0 1 20
+				2 0 0 0
+				0xff 0 0 0>; /*ending*/
+			power_off_step = <
+				2 0 0 50
+				0 0 0 10
+				0 1 1 100
+				0xff 0 0 0>; /*ending*/
+			backlight_index = <0>;
+		};
+
+		lcd_1{
+			model_name = "TV070WSM";
+			interface = "mipi";
+			basic_setting = <600 1024 /*h_active, v_active*/
+				700 1053 /*h_period, v_period*/
+				8 /*lcd_bits*/
+				95 163>; /*screen_widht, screen_height*/
+			lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
+				2 8 0>; /*vs_width,vs_bp,vs_pol*/
+			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+				0 /*clk_ss_level*/
+				1 /*clk_auto_generate*/
+				44250000>; /*pixel_clk(unit in Hz)*/
+			mipi_attr = <4 /*lane_num*/
+				360 /*bit_rate_max(MHz)*/
+				0 /*factor(*100, default 0 for auto)*/
+				1 /*operation_mode_init(0=video, 1=command)*/
+				0 /*operation_mode_display(0=video, 1=command)*/
+				2 /*
+				   *video_mode_type
+				   *(0=sync_pulse,1=sync_event,2=burst)
+				   */
+				0 /*clk_always_hs(0=disable,1=enable)*/
+				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+				/* dsi_init: data_type, num, data... */
+			dsi_init_on = <
+				0xff 10
+				0xf0 3 0 1 30 /* reset high, delay 30ms */
+				0xf0 3 0 0 10 /* reset low, delay 10ms */
+				0xf0 3 0 1 30 /* reset high, delay 30ms */
+				0xfc 2 0x04 3 /* check_reg, check_cnt */
+				0xff 0xff>; /* ending flag */
+			dsi_init_off = <0xff 0xff>; /* ending flag */
+				/* extern_init: 0xff for invalid */
+			extern_init = <1>;
+				/* power step: type,index,value,delay(ms) */
+			power_on_step = <
+					0 1 0 200
+					2 0 0 0
+					0xff 0 0 0>;
+			power_off_step = <
+					2 0 0 0
+					0 0 0 20
+					0 1 1 100
+					0xff 0 0 0>;
+			backlight_index = <0>;
+		};
+
+		lcd_2{
+			model_name = "P070ACB";
+			interface = "mipi";
+			basic_setting = <600 1024 /*h_active, v_active*/
+				680 1194 /*h_period, v_period*/
+				8 /*lcd_bits*/
+				3 5>; /*screen_widht, screen_height*/
+			lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
+				10 80 0>; /*vs_width,vs_bp,vs_pol*/
+			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+				0 /*clk_ss_level*/
+				1 /*clk_auto_generate*/
+				48715200>; /*pixel_clk(unit in Hz)*/
+			mipi_attr = <4 /*lane_num*/
+				400 /*bit_rate_max(MHz)*/
+				0 /*factor(*100, default 0 for auto)*/
+				1 /*operation_mode_init(0=video, 1=command)*/
+				0 /*operation_mode_display(0=video, 1=command)*/
+				2 /*
+				   *video_mode_type
+				   *(0=sync_pulse,1=sync_event,2=burst)
+				   */
+				0 /*clk_always_hs(0=disable,1=enable)*/
+				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+				/* dsi_init: data_type, num, data... */
+			dsi_init_on = <
+				0xff 10
+				0xf0 3 0 1 30 /* reset high, delay 30ms */
+				0xf0 3 0 0 10 /* reset low, delay 10ms */
+				0xf0 3 0 1 30 /* reset high, delay 30ms */
+				0xfc 2 0x04 3 /* check_reg, check_cnt */
+				0xff 0xff>; /* ending flag */
+			dsi_init_off = <0xff 0xff>; /* ending flag */
+				/* extern_init: 0xff for invalid */
+			extern_init = <2>;
+				/* power step: type,index,value,delay(ms) */
+			power_on_step = <
+					0 1 0 200 /* panel power on */
+					2 0 0 0
+					0xff 0 0 0>;
+			power_off_step = <
+					2 0 0 0
+					0 0 0 20  /* reset low */
+					0 1 1 100 /* panel power off */
+					0xff 0 0 0>;
+			backlight_index = <0>;
+		};
+
+		lcd_3{
+			model_name = "TL050FHV02CT";
+			interface = "mipi";
+			basic_setting = <1080 1920 /*h_active, v_active*/
+				1125 2100 /*h_period, v_period*/
+				8 /*lcd_bits*/
+				65 119>; /*screen_widht, screen_height*/
+			lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+				44 108 0>; /*vs_width,vs_bp,vs_pol*/
+			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+				0 /*clk_ss_level*/
+				1 /*clk_auto_generate*/
+				118125000>; /*pixel_clk(unit in Hz)*/
+			mipi_attr = <4 /*lane_num*/
+				960 /*bit_rate_max(MHz)*/
+				0 /*factor(*100, default 0 for auto)*/
+				1 /*operation_mode_init(0=video, 1=command)*/
+				0 /*operation_mode_display(0=video, 1=command)*/
+				2 /*
+				   *video_mode_type
+				   *(0=sync_pulse,1=sync_event,2=burst)
+				   */
+				1 /*clk_always_hs(0=disable,1=enable)*/
+				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+				/* dsi_init: data_type, num, data... */
+			dsi_init_on = <0xff 0xff>; /* ending flag */
+			dsi_init_off = <0xff 0xff>; /* ending flag */
+				/* extern_init: 0xff for invalid */
+			extern_init = <3>;
+				/* power step: type,index,value,delay(ms) */
+			power_on_step = <
+					0 1 0 200
+					0 0 1 20
+					0 0 0 10
+					0 0 1 20
+					2 0 0 0
+					0xff 0 0 0>;
+			power_off_step = <
+					2 0 0 0
+					0 0 0 20
+					0 1 1 100
+					0xff 0 0 0>;
+			backlight_index = <0>;
+		};
+
+		lcd_4{
+			model_name = "TL070WSH27";
+			interface = "mipi";
+			basic_setting = <1024 600 /*h_active, v_active*/
+				1250 630 /*h_period, v_period*/
+				8 /*lcd_bits*/
+				154 86>; /*screen_widht, screen_height*/
+			lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+				5 20 0>; /*vs_width, vs_bp, vs_pol*/
+			clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+				0 /*clk_ss_level */
+				1 /*clk_auto_generate*/
+				47250000>; /*pixel_clk(unit in Hz)*/
+			mipi_attr = <4 /*lane_num*/
+				300 /*bit_rate_max(MHz)*/
+				0 /*factor(*100, default 0 for auto)*/
+				1 /*operation_mode_init(0=video, 1=command)*/
+				0 /*operation_mode_display(0=video, 1=command)*/
+				2 /*
+				   *video_mode_type
+				   *(0=sync_pulse,1=sync_event,2=burst)
+				   */
+				1 /*clk_always_hs(0=disable,1=enable)*/
+				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+			/* dsi_init: data_type, num, data... */
+			dsi_init_on = <0x05 1 0x11
+					0xff 20     /*delay(ms)*/
+					0x05 1 0x29
+					0xff 20     /*delay(ms)*/
+					0xff 0xff>; /*ending*/
+			dsi_init_off = <0x05 1 0x28
+					0xff 10     /*delay(ms)*/
+					0x05 1 0x10
+					0xff 10     /*delay(ms)*/
+					0xff 0xff>; /*ending*/
+			extern_init = <0xff>; /*0xff for invalid*/
+
+			/* power step: type, index, value, delay(ms) */
+			power_on_step = <
+				0 1 0 100
+				0 0 0 10
+				0 0 1 20
+				2 0 0 0
+				0xff 0 0 0>; /*ending*/
+			power_off_step = <
+				2 0 0 50
+				0 0 0 10
+				0 1 1 100
+				0xff 0 0 0>; /*ending*/
+			backlight_index = <0>;
+		};
+	};
+
+	lcd_extern{
+		compatible = "amlogic, lcd_extern";
+		dev_name = "lcd_extern";
+		status = "okay";
+		key_valid = <0>;
+
+		extern_0{
+			index = <0>;
+			extern_name = "mipi_default";/*default*/
+			status = "okay";
+			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+			cmd_size = <0xff>;
+			init_on = <
+				0xff 10
+				0x05 1 0x11
+				0xff 120  /* delay 120ms */
+				0x05 1 0x29
+				0xff 0xff>; /*ending*/
+			init_off = <
+				0x05 1 0x28 /* display off */
+				0xff 10     /* delay 10ms */
+				0x05 1 0x10 /* sleep in */
+				0xff 150      /* delay 150ms */
+				0xff 0xff>; /*ending*/
+		};
+
+		extern_1{
+			index = <1>;
+			extern_name = "mipi_default";/*TV070WSM*/
+			status = "okay";
+			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+			cmd_size = <0xff>;
+			init_on = <
+				0xff 10
+				0x15 2 0x62 0x01
+				0x39 5 0xff 0xaa 0x55 0x25 0x01
+				0x15 2 0xfc 0x08
+				0xff 1   /* delay */
+				0x15 2 0xfc 0x00
+				0x39 5 0xff 0xaa 0x55 0x25 0x00
+				0xff 20   /* delay */
+				0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x00
+				0x39 3 0xb1 0x68 0x41
+				0x15 2 0xb5 0x88
+				0x15 2 0xb6 0x0f
+				0x39 5 0xb8 0x01 0x01 0x12 0x01
+				0x39 3 0xbb 0x11 0x11
+				0x39 3 0xbc 0x05 0x05
+				0x15 2 0xc7 0x03
+				0x39 6 0xbd 0x03 0x02 0x19 0x17 0x00
+				0x15 2 0xc8 0x80
+				0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x01
+				0x39 3 0xB2 0x01 0x01
+				0x39 3 0xB3 0x28 0x28
+				0x39 3 0xB4 0x14 0x14
+				0x39 3 0xB8 0x05 0x05
+				0x39 3 0xB9 0x45 0x45
+				0x39 3 0xBA 0x25 0x25
+				0x39 3 0xBC 0x88 0x00
+				0x39 3 0xBD 0x88 0x00
+				0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x02
+				0x15 2 0xEE 0x00
+				0x39 17 0xB0 0x00 0x4B 0x00 0x5C 0x00
+					0x79 0x00 0x94 0x00 0xA6 0x00 0xD8
+					0x00 0xF2 0x01 0x19
+				0x39 17 0xB1 0x01 0x39 0x01 0x77 0x01
+					0xA2 0x01 0xF2 0x02 0x32 0x02 0x34
+					0x02 0x6D 0x02 0xA2
+				0x39 17 0xB2 0x02 0xC7 0x02 0xF2 0x03
+					0x18 0x03 0x43 0x03 0x65 0x03 0x86
+					0x03 0x8F 0x03 0x94
+				0x39 5 0xB3 0x03 0x96 0x03 0x98
+				0x39 17 0xB4 0x00 0x84 0x00 0x91 0x00
+					0xA4 0x00 0xB6 0x00 0xCA 0x00 0xE9
+					0x01 0x02 0x01 0x2A
+				0x39 17 0xB5 0x01 0x49 0x01 0x82 0x01
+					0xAF 0x01 0xF7 0x02 0x36 0x02 0x38
+					0x02 0x70 0x02 0xA6
+				0x39 17 0xB6 0x02 0xC8 0x02 0xF5 0x03
+					0x1A 0x03 0x43 0x03 0x62 0x03 0x82
+					0x03 0x8F 0x03 0x94
+				0x39 5 0xB7 0x03 0x96 0x03 0x98
+				0x39 17 0xB8 0x01 0x22 0x01 0x27 0x01
+					0x2E 0x01 0x38 0x01 0x40 0x01 0x53
+					0x01 0x60 0x01 0x7B
+				0x39 17 0xB9 0x01 0x8C 0x01 0xB5 0x01
+					0xD3 0x02 0x11 0x02 0x49 0x02 0x4A
+					0x02 0x7F 0x02 0xB1
+				0x39 17 0xBA 0x02 0xD1 0x03 0x00 0x03
+					0x22 0x03 0x49 0x03 0x60 0x03 0x7A
+					0x03 0x8B 0x03 0x8F
+				0x39 5 0xBB 0x03 0x93 0x03 0x9A
+				0x39 17 0xBC 0x00 0x37 0x00 0x48 0x00
+					0x65 0x00 0x80 0x00 0x92 0x00 0xC4
+					0x00 0xDE 0x01 0x05
+				0x39 17 0xBD 0x01 0x31 0x01 0x6F 0x01
+					0x9E 0x01 0xEE 0x02 0x32 0x02 0x34
+					0x02 0x71 0x02 0xA7
+				0x39 17 0xBE 0x02 0xD3 0x02 0xFE 0x03
+					0x24 0x03 0x4F 0x03 0x71 0x03 0x92
+					0x03 0x9B 0x03 0xA0
+				0x39 5 0xBF 0x03 0xA6 0x03 0xA8
+				0x39 17 0xC0 0x00 0x70 0x00 0x7D 0x00
+					0x90 0x00 0xA4 0x00 0xB6 0x00 0xD5
+					0x00 0xEE 0x01 0x16
+				0x39 17 0xC1 0x01 0x41 0x01 0x7A 0x01
+					0xAB 0x01 0xF3 0x02 0x36 0x02 0x38
+					0x02 0x74 0x02 0xAA
+				0x39 17 0xC2 0x02 0xD4 0x03 0x01 0x03
+					0x26 0x03 0x4F 0x03 0x6E 0x03 0x8E
+					0x03 0x9B 0x03 0xA0
+				0x39 5 0xC3 0x03 0xA6 0x03 0xA8
+				0x39 17 0xC4 0x01 0x0E 0x01 0x13 0x01
+					0x1A 0x01 0x24 0x01 0x2C 0x01 0x3F
+					0x01 0x4C 0x01 0x67
+				0x39 17 0xC5 0x01 0x84 0x01 0xAD 0x01
+					0xCF 0x02 0x0D 0x02 0x49 0x02 0x4A
+					0x02 0x83 0x02 0xB5
+				0x39 17 0xC6 0x02 0xDD 0x03 0x0C 0x03
+					0x2E 0x03 0x55 0x03 0x6B 0x03 0x86
+					0x03 0x97 0x03 0x9B
+				0x39 5 0xC7 0x03 0xA1 0x03 0xA8
+				0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x04
+				0x39 6 0xB1 0x03 0x02 0x02 0x02 0x00
+				0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x06
+				0x39 3 0xB0 0x11 0x11
+				0x39 3 0xB1 0x13 0x13
+				0x39 3 0xB2 0x03 0x03
+				0x39 3 0xB3 0x34 0x34
+				0x39 3 0xB4 0x34 0x34
+				0x39 3 0xB5 0x34 0x34
+				0x39 3 0xB6 0x34 0x34
+				0x39 3 0xB7 0x34 0x34
+				0x39 3 0xB8 0x34 0x34
+				0x39 3 0xB9 0x34 0x34
+				0x39 3 0xBA 0x34 0x34
+				0x39 3 0xBB 0x34 0x34
+				0x39 3 0xBC 0x34 0x34
+				0x39 3 0xBD 0x34 0x34
+				0x39 3 0xBE 0x34 0x34
+				0x39 3 0xBF 0x34 0x34
+				0x39 3 0xC0 0x34 0x34
+				0x39 3 0xC1 0x02 0x02
+				0x39 3 0xC2 0x12 0x12
+				0x39 3 0xC3 0x10 0x10
+				0x39 3 0xE5 0x34 0x34
+				0x39 6 0xD8 0x00 0x00 0x00 0x00 0x00
+				0x39 6 0xD9 0x00 0x00 0x00 0x00 0x00
+				0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x05
+				0x15 2 0xC0 0x03
+				0x15 2 0xC1 0x02
+				0x39 3 0xC8 0x01 0x20
+				0x15 2 0xE5 0x03
+				0x15 2 0xE6 0x03
+				0x15 2 0xE7 0x03
+				0x15 2 0xE8 0x03
+				0x15 2 0xE9 0x03
+				0x39 5 0xD1 0x03 0x00 0x3D 0x00
+				0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+				0x39 3 0xB0 0x11 0x00
+				0x39 3 0xB1 0x11 0x00
+				0x39 6 0xB2 0x03 0x00 0x00 0x00 0x00
+				0x39 6 0xB3 0x03 0x00 0x00 0x00 0x00
+				0x39 6 0xBA 0x31 0x00 0x00 0x00 0x00
+				0x15 2 0x35 0x00
+				0x15 2 0x51 0xFF
+				0x15 2 0x53 0x2C
+				0x15 2 0x55 0x03
+				0x05 1 0x11
+				0xff 120  /* delay 120ms */
+				0x05 1 0x29
+				0xff 130   /* delay 130ms */
+				0xFF 0xFF>; /*ending*/
+			init_off = <
+				0x05 1 0x28 /* display off */
+				0xff 10     /* delay 10ms */
+				0x05 1 0x10 /* sleep in */
+				0xff 150      /* delay 150ms */
+				0xff 0xff>; /*ending*/
+		};
+
+		extern_2{
+			index = <2>;
+			extern_name = "mipi_default";/*P070ACB*/
+			status = "okay";
+			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+			cmd_size = <0xff>;
+			init_on = <
+				0x29 5 0xFF 0xAA 0x55 0x25 0x01
+				0x23 2 0xFC 0x08
+				0xFF 1   /* delay(ms) */
+				0x23 2 0xFC 0x00
+				0xFF 1  /* delay(ms) */
+				0x23 2 0x6F 0x21
+				0x23 2 0xF7 0x01
+				0xFF 1   /* delay(ms) */
+				0x23 2 0x6F 0x21
+				0x23 2 0xF7 0x00
+				0xFF 1	   /* delay(ms) */
+
+				0x23 2 0x6F 0x1A
+				0x23 2 0xF7 0x05
+				0xFF 1	   /* delay(ms) */
+
+				0x29 5 0xFF 0xAA 0x55 0x25 0x00
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+				0x29 3 0xB1 0x68 0x41
+				0x23 2 0xB5 0x88
+				0x29 6 0xBD 0x02 0xB0 0x0C 0x14 0x00
+				0x23 2 0xC8 0x80
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+				0x29 3 0xB3 0x2D 0x2D
+				0x29 3 0xB4 0x19 0x19
+				0x23 2 0xB5 0x06
+
+				0x29 3 0xB9 0x36 0x36
+				0x29 3 0xBA 0x26 0x26
+				0x29 3 0xBC 0xA8 0x01
+				0x29 3 0xBD 0xAB 0x01
+				0x23 2 0xC0 0x0C
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x02
+				0x23 2 0xEE 0x02
+				0x29 7 0xB0 0x00 0x50 0x00 0x52 0x00 0x73
+				0x23 2 0x6F 0x06
+				0x29 7 0xB0 0x00 0x8F 0x00 0xA5 0x00 0xCA
+				0x23 2 0x6F 0x0C
+				0x29 5 0xB0 0x00 0xEA 0x01 0x1B
+				0x29 7 0xB1 0x01 0x42 0x01 0x82 0x01 0xB3
+				0x23 2 0x6F 0x06
+				0x29 7 0xB1 0x02 0x00 0x02 0x41 0x02 0x42
+				0x23 2 0x6F 0x0C
+				0x29 5 0xB1 0x02 0x78 0x02 0xB5
+				0x29 7 0xB2 0x02 0xDA 0x03 0x12 0x03 0x3A
+				0x23 2 0x6F 0x06
+				0x29 7 0xB2 0x03 0x6E 0x03 0x8D 0x03 0xB1
+				0x23 2 0x6F 0x0C
+				0x29 5 0xB2 0x03 0xCA 0x03 0xE8
+				0x29 5 0xB3 0x03 0xF4 0x03 0xFF
+
+				0x29 7 0xBC 0x00 0x05 0x00 0x52 0x00 0x73
+				0x23 2 0x6F 0x06
+				0x29 7 0xBC 0x00 0x8F 0x00 0xA5 0x00 0xCA
+				0x23 2 0x6F 0x0C
+				0x29 5 0xBC 0x00 0xEA 0x01 0x1B
+				0x29 7 0xBD 0x01 0x42 0x01 0x82 0x01 0xB3
+				0x23 2 0x6F 0x06
+				0x29 7 0xBD 0x02 0x00 0x02 0x41 0x02 0x42
+				0x23 2 0x6F 0x0C
+				0x29 5 0xBD 0x02 0x78 0x02 0xB5
+				0x29 7 0xBE 0x02 0xDA 0x03 0x12 0x03 0x3A
+				0x23 2 0x6F 0x06
+				0x29 7 0xBE 0x03 0x6E 0x03 0x8D 0x03 0xB1
+				0x23 2 0x6F 0x0C
+				0x29 5 0xBE 0x03 0xCA 0x03 0xE8
+				0x29 5 0xBF 0x03 0xF4 0x03 0xFF
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+				0x29 6 0xB2 0x05 0x00 0x00 0x00 0x00
+				0x29 6 0xB6 0x05 0x00 0x00 0x00 0x00
+				0x29 6 0xB7 0x05 0x00 0x00 0x00 0x00
+				0x29 6 0xBA 0x57 0x00 0x00 0x00 0x00
+				0x29 6 0xBB 0x57 0x00 0x00 0x00 0x00
+				0x29 5 0xC0 0x00 0x34 0x00 0x00
+				0x29 5 0xC1 0x00 0x00 0x34 0x00
+				0x23 2 0xC4 0x40
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x05
+				0x29 3 0xB0 0x17 0x06
+				0x29 3 0xB1 0x17 0x06
+				0x29 3 0xB2 0x17 0x06
+				0x29 3 0xB3 0x17 0x06
+				0x29 3 0xB4 0x17 0x06
+
+				0x29 6 0xBD 0x03 0x01 0x03 0x03 0x01
+				0x23 2 0xC0 0x05
+				0x23 2 0xC4 0x82
+				0x23 2 0xC5 0xA2
+				0x29 3 0xC8 0x03 0x30
+				0x29 3 0xC9 0x03 0x31
+				0x29 4 0xCC 0x00 0x00 0x3C
+				0x29 4 0xCD 0x00 0x00 0x3C
+				0x29 6 0xD1 0x00 0x44 0x09 0x00 0x00
+				0x29 6 0xD2 0x00 0x04 0x0B 0x00 0x00
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x06
+				0x29 3 0xB0 0x0B 0x2D
+				0x29 3 0xB1 0x2D 0x09
+				0x29 3 0xB2 0x2A 0x29
+				0x29 3 0xB3 0x34 0x1B
+				0x29 3 0xB4 0x19 0x17
+				0x29 3 0xB5 0x15 0x13
+				0x29 3 0xB6 0x11 0x01
+				0x29 3 0xB7 0x34 0x34
+				0x29 3 0xB8 0x34 0x2D
+				0x29 3 0xB9 0x2D 0x34
+				0x29 3 0xBA 0x2D 0x2D
+				0x29 3 0xBB 0x34 0x34
+				0x29 3 0xBC 0x34 0x34
+				0x29 3 0xBD 0x00 0x10
+				0x29 3 0xBE 0x12 0x14
+				0x29 3 0xBF 0x16 0x18
+
+				0x29 3 0xC0 0x1A 0x34
+				0x29 3 0xC1 0x29 0x2A
+				0x29 3 0xC2 0x08 0x2D
+				0x29 3 0xC3 0x2D 0x0A
+				0x29 3 0xC4 0x0A 0x2D
+				0x29 3 0xC5 0x2D 0x00
+				0x29 3 0xC6 0x2A 0x29
+				0x29 3 0xC7 0x34 0x14
+				0x29 3 0xC8 0x16 0x18
+				0x29 3 0xC9 0x1A 0x10
+				0x29 3 0xCA 0x12 0x08
+				0x29 3 0xCB 0x34 0x34
+				0x29 3 0xCC 0x34 0x2D
+				0x29 3 0xCD 0x2D 0x34
+				0x29 3 0xCE 0x2D 0x2D
+				0x29 3 0xCF 0x34 0x34
+
+				0x29 3 0xD0 0x34 0x34
+				0x29 3 0xD1 0x09 0x13
+				0x29 3 0xD2 0x11 0x1B
+				0x29 3 0xD3 0x19 0x17
+				0x29 3 0xD4 0x15 0x34
+				0x29 3 0xD5 0x29 0x2A
+				0x29 3 0xD6 0x01 0x2D
+				0x29 3 0xD7 0x2D 0x0B
+				0x29 6 0xD8 0x00 0x00 0x00 0x00 0x00
+				0x29 6 0xD9 0x00 0x00 0x00 0x00 0x00
+
+				0x29 3 0xE5 0x34 0x34
+				0x29 3 0xE6 0x34 0x34
+				0x23 2 0xE7 0x00
+				0x29 3 0xE8 0x34 0x34
+				0x29 3 0xE9 0x34 0x34
+				0x23 2 0xEA 0x00
+
+				0x29 6 0xF0 0x55 0xAA 0x52 0x00 0x00
+
+				0x13 1 0x35
+				0x13 1 0x11
+				0xFF 120   /* delay(ms) */
+				0x13 1 0x29
+				0xFF 20    /* delay(ms) */
+				0xFF 0xFF>; /*ending*/
+			init_off = <
+				0x05 1 0x28 /* display off */
+				0xff 10     /* delay 10ms */
+				0x05 1 0x10 /* sleep in */
+				0xff 150      /* delay 150ms */
+				0xff 0xff>; /*ending*/
+		};
+
+		extern_3{
+			index = <3>;
+			extern_name = "mipi_default";/*TL050FHV02CT*/
+			status = "okay";
+			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+			cmd_size = <0xff>;
+			init_on = <
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+				0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+					0x00 0x38 0x00 0x00
+				0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+					0x00 0x00 0x00 0x00
+				0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+					0x00 0x38 0x00 0x10 0x03 0x04
+				0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+					0x03 0xD3 0x0C
+				0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+					0x00 0x00 0x00 0x00 0x00 0x00 0x00
+					0x00 0x00 0x00 0x00
+				0x29 3 0x99 0x00 0x00
+				0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+					0x00 0x00 0x00 0x00 0x00 0x00
+				0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+				0x29 3 0x9C 0x00 0x00
+				0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+					0x10 0x00 0x00
+				0x29 3 0x9E 0x00 0x00
+				0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+					0x1F 0x00 0x1F 0x14 0x1F
+				0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x15
+				0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+					0x0B 0x1F 0x09 0x1F 0x1F
+				0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+					0x1F 0x01 0x1F 0x15 0x1F
+				0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x1F
+				0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+					0x1F 0x1F 0x1F 0x1F 0x14
+				0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+					0x08 0x1F 0x0A 0x1F 0x1F
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+				0x29 4 0xBC 0x00 0x00 0x00
+				0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+				0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+				0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+				0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+				0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+				0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+				0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+				0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+					0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+					0x00 0x79 0x00 0xA7
+				0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+					0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+					0x02 0x2F 0x02 0x74
+				0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+					0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+					0x03 0x8C 0x03 0xA5
+				0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+				0x29 4 0xB0 0x05 0x05 0x05
+				0x29 4 0xB1 0x05 0x05 0x05
+				0x29 4 0xB3 0x10 0x10 0x10
+				0x29 4 0xB4 0x06 0x06 0x06
+				0x29 4 0xB6 0x44 0x44 0x44
+				0x29 4 0xB7 0x34 0x34 0x34
+				0x29 4 0xB8 0x34 0x34 0x34
+				0x29 4 0xB9 0x24 0x24 0x24
+				0x29 4 0xBA 0x24 0x24 0x24
+				0x29 4 0xBC 0x00 0x70 0x00
+				0x29 4 0xBD 0x00 0x70 0x00
+				0x23 2 0xBE 0x50
+				0x23 2 0x35 0x00
+				0x13 1 0x11
+				0xff 200
+				0x13 1 0x29
+				0xff 200
+				0xFF 0xFF>; /*ending*/
+			init_off = <
+				0x05 1 0x28 /* display off */
+				0xff 10     /* delay 10ms */
+				0x05 1 0x10 /* sleep in */
+				0xff 150    /* delay 150ms */
+				0xff 0xff>; /*ending*/
+		};
+
+	};
+
+	backlight{
+		compatible = "amlogic, backlight-g12b";
+		dev_name = "backlight";
+		status = "okay";
+		key_valid = <0>;
+		pinctrl-names = "pwm_on";
+		pinctrl-0 = <&pwm_f_pins2>;
+		pinctrl_version = <2>; /* for uboot */
+		bl_pwm_config = <&bl_pwm_conf>;
+		bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+			&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+		bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+		/* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+		/* power index:(point gpios_index, 0xff=invalid)
+		 * power value:(0=output low, 1=output high, 2=input)
+		 * power delay:(unit in ms)
+		 */
+
+		backlight_0{
+			index = <0>;
+			bl_name = "backlight_pwm";
+			bl_level_default_uboot_kernel = <100 100>;
+			bl_level_attr = <255 10 /*max, min*/
+				128 128>; /*mid, mid_mapping*/
+			bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+			bl_power_attr = <0 /*en_gpio_index*/
+				1 0 /*on_value, off_value*/
+				200 200>; /*on_delay(ms), off_delay(ms)*/
+			bl_pwm_port = "PWM_F";
+			bl_pwm_attr = <0 /*pwm_method*/
+				180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+				100 25>; /*duty_max(%), duty_min(%)*/
+			bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+				10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+			bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+		};
+		backlight_1{
+			index = <1>;
+			bl_name = "bl_extern";
+			bl_level_default_uboot_kernel = <100 100>;
+			bl_level_attr = <255 10 /*max, min*/
+				128 128>; /*mid, mid_mapping*/
+			bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+			bl_power_attr = <1 /*en_gpio_index*/
+				1 0 /*on_value, off_value*/
+				200 200>; /*on_delay(ms), off_delay(ms)*/
+			bl_extern_index = <0>;
+		};
+	};
+	bl_pwm_conf:bl_pwm_conf{
+		pwm_channel_0 {
+			pwm_port_index = <5>;
+			pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+		};
+	};
+	bl_extern{
+		compatible = "amlogic, bl_extern";
+		dev_name = "bl_extern";
+		status = "disabled";
+		extern_0{
+			index = <0>;
+			extern_name = "i2c_lp8556";
+			type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+			i2c_address = <0x2c>; /*7bit i2c address*/
+			i2c_bus = "i2c_bus_c";
+			dim_max_min = <255 10>;
+		};
+		extern_1{
+			index = <1>;
+			extern_name = "mipi_lt070me05";
+			type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+			dim_max_min = <255 10>;
+		};
+	};
+};/* end of panel */
+
diff --git a/drivers/amlogic/media/vout/backlight/aml_bl.c b/drivers/amlogic/media/vout/backlight/aml_bl.c
index 06e7b87bf2c7..751a9bffeef7 100644
--- a/drivers/amlogic/media/vout/backlight/aml_bl.c
+++ b/drivers/amlogic/media/vout/backlight/aml_bl.c
@@ -3001,6 +3001,12 @@ static struct bl_data_s bl_data_g12a = {
 	.pwm_reg = pwm_reg_txlx,
 };
 
+static struct bl_data_s bl_data_g12b = {
+	.chip_type = BL_CHIP_G12B,
+	.chip_name = "g12b",
+	.pwm_reg = pwm_reg_txlx,
+};
+
 static const struct of_device_id bl_dt_match_table[] = {
 	{
 		.compatible = "amlogic, backlight-gxtvbb",
@@ -3026,6 +3032,10 @@ static const struct of_device_id bl_dt_match_table[] = {
 		.compatible = "amlogic, backlight-g12a",
 		.data = &bl_data_g12a,
 	},
+	{
+		.compatible = "amlogic, backlight-g12b",
+		.data = &bl_data_g12b,
+	},
 	{},
 };
 #endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
index 7e9c215d8ae3..cd5121decb64 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
@@ -139,6 +139,7 @@ static void lcd_clk_config_init_print(void)
 	switch (lcd_drv->data->chip_type) {
 	case LCD_CHIP_AXG:
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		LCDPR("lcd clk config init:\n"
 			"pll_m_max:         %d\n"
 			"pll_m_min:         %d\n"
@@ -202,6 +203,7 @@ int lcd_clk_config_print(char *buf, int offset)
 	n = lcd_debug_info_len(len + offset);
 	switch (lcd_drv->data->chip_type) {
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) {
 			len += snprintf((buf+len), n,
 				"lcd clk config:\n"
@@ -395,6 +397,7 @@ static void lcd_clk_config_chip_init(void)
 		cConf->xd_out_fmax = ENCL_CLK_IN_MAX_AXG;
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) {
 			cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A;
 			cConf->ss_level_max = SS_LEVEL_MAX_GP0_G12A;
@@ -437,6 +440,7 @@ int lcd_clk_path_change(int sel)
 
 	switch (lcd_drv->data->chip_type) {
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (sel) {
 			lcd_drv->lcd_clk_path = 1;
 			cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A;
@@ -1099,6 +1103,7 @@ static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf)
 	/* select vid_pll_clk */
 	switch (lcd_drv->data->chip_type) {
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path)
 			lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_CLK_IN_SEL, 3);
 		else
@@ -2111,6 +2116,7 @@ void lcd_clk_generate_parameter(struct lcd_config_s *pconf)
 		lcd_clk_generate_axg(pconf);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path)
 			lcd_clk_generate_axg(pconf);
 		else
@@ -2202,6 +2208,7 @@ void lcd_pll_reset(void)
 		lcd_pll_reset_axg();
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path)
 			lcd_gp0_pll_reset_g12a();
 		else
@@ -2239,6 +2246,7 @@ void lcd_clk_update(struct lcd_config_s *pconf)
 		lcd_update_pll_frac_axg(&clk_conf);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) {
 			lcd_pll_frac_generate_axg(pconf);
 			lcd_update_gp0_pll_frac_g12a(&clk_conf);
@@ -2283,6 +2291,7 @@ void lcd_clk_set(struct lcd_config_s *pconf)
 		lcd_set_pll_axg(&clk_conf);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) { /* gp0_pll */
 			lcd_set_gp0_pll_g12a(&clk_conf);
 			lcd_set_dsi_phy_clk(1);
@@ -2331,6 +2340,7 @@ void lcd_clk_disable(void)
 		lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 0, LCD_PLL_EN_AXG, 1);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) {
 			lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A,
 				0, LCD_PLL_EN_GP0_G12A, 1);
@@ -2382,6 +2392,7 @@ void lcd_clk_gate_switch(int status)
 				clk_prepare_enable(lcd_drv->mipi_bandgap_gate);
 			break;
 		case LCD_CHIP_G12A:
+		case LCD_CHIP_G12B:
 			if (IS_ERR(lcd_drv->dsi_host_gate))
 				LCDERR("%s: dsi_host_gate\n", __func__);
 			else
@@ -2450,6 +2461,7 @@ void lcd_clk_gate_switch(int status)
 					lcd_drv->mipi_bandgap_gate);
 			break;
 		case LCD_CHIP_G12A:
+		case LCD_CHIP_G12B:
 			if (IS_ERR(lcd_drv->dsi_host_gate))
 				LCDERR("%s: dsi_host_gate\n", __func__);
 			else
@@ -2527,6 +2539,7 @@ static void lcd_clktree_probe(void)
 			LCDERR("%s: clk mipi_bandgap_gate\n", __func__);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		lcd_drv->dsi_host_gate = devm_clk_get(lcd_drv->dev,
 			"dsi_host_gate");
 		if (IS_ERR(lcd_drv->dsi_host_gate))
@@ -2589,6 +2602,7 @@ static void lcd_clktree_remove(void)
 			devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate);
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (!IS_ERR(lcd_drv->dsi_host_gate))
 			devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate);
 		if (!IS_ERR(lcd_drv->dsi_phy_gate))
diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c
index bc2c481ba484..44ad2ef29dbd 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_debug.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c
@@ -868,6 +868,7 @@ static int lcd_reg_print(char *buf, int offset)
 		}
 		break;
 	case LCD_CHIP_G12A:
+	case LCD_CHIP_G12B:
 		if (lcd_drv->lcd_clk_path) {
 			for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_gp0_g12a);
 				i++) {
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
index 3dfad10ae5df..f749d32fe103 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
@@ -162,6 +162,7 @@ static void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status)
 	if (status) {
 		switch (lcd_drv->data->chip_type) {
 		case LCD_CHIP_G12A:
+		case LCD_CHIP_G12B:
 			/* HHI_MIPI_CNTL0 */
 			/* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
 			lcd_hiu_write(HHI_MIPI_CNTL0,
@@ -221,6 +222,7 @@ static void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status)
 	} else {
 		switch (lcd_drv->data->chip_type) {
 		case LCD_CHIP_G12A:
+		case LCD_CHIP_G12B:
 			lcd_hiu_write(HHI_MIPI_CNTL0, 0);
 			lcd_hiu_write(HHI_MIPI_CNTL1, 0);
 			lcd_hiu_write(HHI_MIPI_CNTL2, 0);
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c
index 7bc8f45bb857..6d6a783975c7 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_vout.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c
@@ -960,6 +960,12 @@ static struct lcd_data_s lcd_data_g12a = {
 	.reg_map_table = &lcd_reg_axg[0],
 };
 
+static struct lcd_data_s lcd_data_g12b = {
+	.chip_type = LCD_CHIP_G12B,
+	.chip_name = "g12b",
+	.reg_map_table = &lcd_reg_axg[0],
+};
+
 static const struct of_device_id lcd_dt_match_table[] = {
 	{
 		.compatible = "amlogic, lcd-gxtvbb",
@@ -985,6 +991,10 @@ static const struct of_device_id lcd_dt_match_table[] = {
 		.compatible = "amlogic, lcd-g12a",
 		.data = &lcd_data_g12a,
 	},
+	{
+		.compatible = "amlogic, lcd-g12b",
+		.data = &lcd_data_g12b,
+	},
 	{},
 };
 #endif
diff --git a/include/linux/amlogic/media/vout/lcd/aml_bl.h b/include/linux/amlogic/media/vout/lcd/aml_bl.h
index 2afb5f1d780b..00b36c6acb11 100644
--- a/include/linux/amlogic/media/vout/lcd/aml_bl.h
+++ b/include/linux/amlogic/media/vout/lcd/aml_bl.h
@@ -48,6 +48,7 @@ enum bl_chip_type_e {
 	BL_CHIP_TXLX,
 	BL_CHIP_AXG,
 	BL_CHIP_G12A,
+	BL_CHIP_G12B,
 	BL_CHIP_MAX,
 };
 
diff --git a/include/linux/amlogic/media/vout/lcd/lcd_vout.h b/include/linux/amlogic/media/vout/lcd/lcd_vout.h
index c7b044177121..32304111b4f3 100644
--- a/include/linux/amlogic/media/vout/lcd/lcd_vout.h
+++ b/include/linux/amlogic/media/vout/lcd/lcd_vout.h
@@ -81,6 +81,7 @@ enum lcd_chip_e {
 	LCD_CHIP_TXLX,  /* 3 */
 	LCD_CHIP_AXG,   /* 4 */
 	LCD_CHIP_G12A,  /* 5 */
+	LCD_CHIP_G12B,  /* 6 */
 	LCD_CHIP_MAX,
 };