From 3aa5acec15556410bd3ab3138e074d41c2698474 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 10 May 2023 09:29:33 +0800 Subject: [PATCH 1/4] drm/rockchip: vop2: move crtc_clock check to mode_fixup for rk3528 Signed-off-by: Damon Ding Change-Id: I207dbe09f17991e9a107cc2df5e7b130600be7b7 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 21 ++++++++++---------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 5d16a85b2e52..f765f6011636 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -6856,6 +6856,14 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) adj_mode->crtc_clock *= 2; + /* + * For RK3528, the path of CVBS output is like: + * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC + * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs. + */ + if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656) + adj_mode->crtc_clock *= 4; + if (vp->mcu_timing.mcu_pix_total) adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(vcstate->bus_format) * (vp->mcu_timing.mcu_pix_total + 1); @@ -8111,17 +8119,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n", __clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk)); } else { - /* - * For RK3528, the path of CVBS output is like: - * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC - * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs. - */ - if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656) - rockchip_drm_dclk_set_rate(vop2->version, vp->dclk, - 4 * adjusted_mode->crtc_clock * 1000); - else - rockchip_drm_dclk_set_rate(vop2->version, vp->dclk, - adjusted_mode->crtc_clock * 1000); + rockchip_drm_dclk_set_rate(vop2->version, vp->dclk, + adjusted_mode->crtc_clock * 1000); } if (vp_data->feature & VOP_FEATURE_OVERSCAN) From 7c4a3b6468fcb14e8e8e7541915e76e65ffe20cc Mon Sep 17 00:00:00 2001 From: Rimon Xu Date: Tue, 5 Dec 2023 18:02:44 +0800 Subject: [PATCH 2/4] video: rockchip: vtunnel: do not fput fence file after fd install Signed-off-by: Rimon Xu Change-Id: I2d596aa981dac5a32267f4f08935fb0401186ead --- drivers/video/rockchip/vtunnel/rkvtunnel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/rockchip/vtunnel/rkvtunnel.c b/drivers/video/rockchip/vtunnel/rkvtunnel.c index 2068e3f05357..2a879ab5f83d 100644 --- a/drivers/video/rockchip/vtunnel/rkvtunnel.c +++ b/drivers/video/rockchip/vtunnel/rkvtunnel.c @@ -1139,6 +1139,9 @@ rkvt_acquire_buf(struct rkvt_buf_data *data, struct rkvt_session *session) goto no_memory; fd_install(fd, buffer->ready_render_fence); buffer->base.fence_fd = fd; + buffer->ready_render_fence = NULL; + } else { + buffer->base.fence_fd = -1; } buffer->base.vt_id = inst->id; data->base = buffer->base; From 371e924377a75a1cf238b1da2ef6e64ed471836a Mon Sep 17 00:00:00 2001 From: Li Hangyu Date: Tue, 12 Dec 2023 18:10:29 +0800 Subject: [PATCH 3/4] ARM: dts: rockchip: rv1106-mcu-v20: Added MCU panel general configuration Separate some configuration items of "rv1106g-evb1-mcu-display-v20.dts" so that they can be used as common configurations Change-Id: I72323b9342235f1c1e9b1c131ead3aabbe9dd51e Signed-off-by: Li Hangyu --- arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi | 266 +++++++++++++++ .../boot/dts/rv1106g-evb1-mcu-display-v20.dts | 302 +----------------- 2 files changed, 267 insertions(+), 301 deletions(-) create mode 100644 arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi diff --git a/arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi new file mode 100644 index 000000000000..6346ba8eb9df --- /dev/null +++ b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ +#include + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0>; + }; + }; +}; + +&display_subsystem { + status = "okay"; + logo-memory-region = <&drm_logo>; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + pinctrl-names = "default"; + /* + * rgb3x8_pins for RGB3x8(8bit) + * rgb565_pins for RGB565(16bit) + */ + pinctrl-0 = <&rgb3x8_pins>; + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + */ + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + 00 00 01 c1 + 01 00 01 41 + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + 00 00 01 36 + 01 00 01 48 + 00 00 01 3a + 01 00 01 66 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ + 00 00 01 b0 + 01 00 01 00 + 00 00 01 b1 + 01 00 01 70 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + 00 00 01 b7 + 01 00 01 c6 + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + 00 00 01 e9 + 01 00 01 00 + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + kd050fwfba002_timing: timing0 { + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <7840125>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "disabled"; +}; + +&vop { + status = "okay"; + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rv1103/rv1106. + */ + mcu-timing { + mcu-pix-total = <5>; + mcu-cs-pst = <1>; + mcu-cs-pend = <4>; + mcu-rw-pst = <2>; + mcu-rw-pend = <3>; + mcu-hold-mode = <0>; // default set to 0 + }; +}; diff --git a/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts b/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts index 21dbea71e3a7..d2c2cd1b7765 100644 --- a/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts +++ b/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts @@ -5,310 +5,10 @@ /dts-v1/; -#include #include "rv1106g-evb1-v11.dts" +#include "rv1106-evb-ext-mcu-v10.dtsi" / { model = "Rockchip RV1106G EVB1 V11 Board + RK EVB MCU 8BIT Display V20 Ext Board"; compatible = "rockchip,rv1106g-evb1-mcu-display-v20", "rockchip,rv1106"; - - backlight: backlight { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm3 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - inactive; - reusable; - size = <0x1000000>; - linux,cma-default; - }; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0>; - }; - }; -}; - -&display_subsystem { - status = "okay"; - logo-memory-region = <&drm_logo>; -}; - -&pwm3 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm3m1_pins>; -}; - -&rgb { - status = "okay"; - rockchip,data-sync-bypass; - pinctrl-names = "default"; - /* - * rgb3x8_pins for RGB3x8(8bit) - * rgb565_pins for RGB565(16bit) - */ - pinctrl-0 = <&rgb3x8_pins>; - - /* - * 320x480 RGB/MCU screen K350C4516T - */ - mcu_panel: mcu-panel { - /* - * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) - * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) - */ - bus-format = ; - backlight = <&backlight>; - enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - enable-delay-ms = <20>; - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - reset-delay-ms = <10>; - prepare-delay-ms = <20>; - unprepare-delay-ms = <20>; - disable-delay-ms = <20>; - init-delay-ms = <10>; - width-mm = <217>; - height-mm = <136>; - - // type:0 is cmd, 1 is data - panel-init-sequence = [ - //type delay num val1 val2 val3 - 00 00 01 e0 - 01 00 01 00 - 01 00 01 07 - 01 00 01 0f - 01 00 01 0d - 01 00 01 1b - 01 00 01 0a - 01 00 01 3c - - 01 00 01 78 - 01 00 01 4a - 01 00 01 07 - 01 00 01 0e - 01 00 01 09 - 01 00 01 1b - 01 00 01 1e - 01 00 01 0f - - 00 00 01 e1 - 01 00 01 00 - 01 00 01 22 - 01 00 01 24 - 01 00 01 06 - 01 00 01 12 - 01 00 01 07 - 01 00 01 36 - - 01 00 01 47 - 01 00 01 47 - 01 00 01 06 - 01 00 01 0a - 01 00 01 07 - 01 00 01 30 - 01 00 01 37 - 01 00 01 0f - - 00 00 01 c0 - 01 00 01 10 - 01 00 01 10 - - 00 00 01 c1 - 01 00 01 41 - - 00 00 01 c5 - 01 00 01 00 - 01 00 01 22 - 01 00 01 80 - - 00 00 01 36 - 01 00 01 48 - - 00 00 01 3a - 01 00 01 66 /* - * interface pixel format: - * 66 for RGB3x8(8bit) - * 55 for RGB565(16bit) - */ - - 00 00 01 b0 - 01 00 01 00 - - 00 00 01 b1 - 01 00 01 70 /* - * frame rate control: - * 70 (45hz) for RGB3x8(8bit) - * a0 (60hz) for RGB565(16bit) - */ - 01 00 01 11 - 00 00 01 b4 - 01 00 01 02 - 00 00 01 B6 - 01 00 01 02 /* - * display function control: - * 32 for RGB - * 02 for MCU - */ - 01 00 01 02 - - 00 00 01 b7 - 01 00 01 c6 - - 00 00 01 be - 01 00 01 00 - 01 00 01 04 - - 00 00 01 e9 - 01 00 01 00 - - 00 00 01 f7 - 01 00 01 a9 - 01 00 01 51 - 01 00 01 2c - 01 00 01 82 - - 00 78 01 11 - 00 32 01 29 - 00 00 01 2c - ]; - - panel-exit-sequence = [ - //type delay num val1 val2 val3 - 00 0a 01 28 - 00 78 01 10 - ]; - - display-timings { - native-mode = <&kd050fwfba002_timing>; - - kd050fwfba002_timing: timing0 { - /* - * 7840125 for frame rate 45Hz - * 10453500 for frame rate 60Hz - */ - clock-frequency = <7840125>; - hactive = <320>; - vactive = <480>; - hback-porch = <10>; - hfront-porch = <5>; - vback-porch = <10>; - vfront-porch = <5>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <1>; - }; - }; - - port { - panel_in_rgb: endpoint { - remote-endpoint = <&rgb_out_panel>; - }; - }; - }; - - ports { - rgb_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vop { - status = "okay"; -}; - -&route_rgb { - status = "disabled"; -}; - -/* - * The pins of sdmmc1 and lcd are multiplexed - */ -&sdio { - status = "disabled"; -}; - -&sdio_pwrseq { - status = "disabled"; -}; - -&vop { - status = "okay"; - - /* - * Default config is as follows: - * - * mcu-pix-total = <9>; - * mcu-cs-pst = <1>; - * mcu-cs-pend = <8>; - * mcu-rw-pst = <2>; - * mcu-rw-pend = <5>; - * mcu-hold-mode = <0>; // default set to 0 - * - * To increase the frame rate, reduce all parameters because - * the max dclk rate of mcu is 150M in rv1103/rv1106. - */ - mcu-timing { - mcu-pix-total = <5>; - mcu-cs-pst = <1>; - mcu-cs-pend = <4>; - mcu-rw-pst = <2>; - mcu-rw-pend = <3>; - - mcu-hold-mode = <0>; // default set to 0 - }; }; From b7adbc93a7494e848e11897db39f917c5874b445 Mon Sep 17 00:00:00 2001 From: Li Hangyu Date: Tue, 12 Dec 2023 17:26:52 +0800 Subject: [PATCH 4/4] ARM: dts: rockchip: rv1106g-cvr: Supports dual-channel sensors Change-Id: Ifdadb74d6670d18de4299d179c6c6dd72cb70316 Signed-off-by: Li Hangyu --- arch/arm/boot/dts/Makefile | 2 +- ...ual-sensor.dts => rv1106g-evb1-v11-cvr-ext-dual-cam.dts} | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) rename arch/arm/boot/dts/{rv1106g-evb1-v11-ext-dual-sensor.dts => rv1106g-evb1-v11-cvr-ext-dual-cam.dts} (97%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e33a72229955..f9fbc45f29d9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1001,7 +1001,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-evb1-v10-spi-nand.dtb \ rv1106g-evb1-v10-spi-nor.dtb \ rv1106g-evb1-v11-nofastae-spi-nand.dtb \ - rv1106g-evb1-v11-ext-dual-sensor.dtb \ + rv1106g-evb1-v11-cvr-ext-dual-cam.dtb \ rv1106g-evb2-v10.dtb \ rv1106g-evb2-v10-dual-camera.dtb \ rv1106g-evb2-v11-emmc.dtb \ diff --git a/arch/arm/boot/dts/rv1106g-evb1-v11-ext-dual-sensor.dts b/arch/arm/boot/dts/rv1106g-evb1-v11-cvr-ext-dual-cam.dts similarity index 97% rename from arch/arm/boot/dts/rv1106g-evb1-v11-ext-dual-sensor.dts rename to arch/arm/boot/dts/rv1106g-evb1-v11-cvr-ext-dual-cam.dts index 9ce575e4f8ea..79b0e99547e1 100644 --- a/arch/arm/boot/dts/rv1106g-evb1-v11-ext-dual-sensor.dts +++ b/arch/arm/boot/dts/rv1106g-evb1-v11-cvr-ext-dual-cam.dts @@ -7,6 +7,7 @@ #include "rv1106.dtsi" #include "rv1106-evb-v10.dtsi" +#include "rv1106-evb-ext-mcu-v20.dtsi" #include "rv1106g-dual-sensor-extboard.dtsi" / { @@ -115,6 +116,11 @@ }; }; +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + &sdio { max-frequency = <200000000>; no-sd;