From 32c3a8cf9cef461f8badaab9969df8ddc5b8957f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 14 May 2018 16:09:52 +0800 Subject: [PATCH] clk: rockchip: rk3288: export PCLK_PD_PMU and PCLK_PD_ALIVE clock id Change-Id: Ie0550d9528367fa070328562fad2e597a5d6d7f7 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3288.c | 4 ++-- include/dt-bindings/clock/rk3288-cru.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index babc595c7a69..f82084fefc50 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -474,9 +474,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), - DIV(0, "pclk_pd_alive", "gpll", 0, + DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", 0, RK3288_CLKSEL_CON(33), 8, 5, DFLAGS), - COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(PCLK_PD_PMU, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(33), 0, 5, DFLAGS, RK3288_CLKGATE_CON(5), 8, GFLAGS), diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 75df8524a620..1f9c62f07389 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -182,6 +182,8 @@ #define PCLK_ISP_IN 371 #define PCLK_VIP 372 #define PCLK_VIP_IN 373 +#define PCLK_PD_ALIVE 374 +#define PCLK_PD_PMU 375 /* hclk gates */ #define HCLK_GPS 448