From 347d284ff834875fdc79d066cff2806d8c1b9bdf Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Mon, 18 Jul 2022 09:50:03 +0800 Subject: [PATCH] phy: rockchip: naneng-combophy: adjust ssc ppm parameter for sata Set the PLL SCC ppm adjust signal to 3500ppm for better compatibility. Signed-off-by: Yifeng Zhao Change-Id: I80aca9cd53aa08944bb929156dc9474118679b47 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 6964c473611d..14e3667597e2 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -802,6 +802,12 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) val &= ~GENMASK(7, 4); val |= 0x50; writel(val, priv->mmio + (0x1f << 2)); + + /* ssc ppm adjust to 3500ppm */ + val = readl(priv->mmio + (0x9 << 2)); + val &= ~GENMASK(3, 0); + val |= 0x7; + writel(val, priv->mmio + (0x9 << 2)); } break; default: