From 347e6b3e3df0600f890580aa72e66ba19cf0f77c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 26 Nov 2021 14:52:49 +0800 Subject: [PATCH] clk: rockchip: rk3588: fix usb3\sata\gamc\pcie aclk parent aclk dependencies: aclk_usb3/satax/gmac --> aclk_mmu_php --> aclk_php_root --> aclk_pcie_root aclk_pciex_mst --> aclk_mmu_pcie --> aclk_pcie_bridge --> aclk_pcie_root --> aclk_php_root Signed-off-by: Elaine Zhang Change-Id: I51933de0e401f6fc381ea177943bde16ca00401a --- drivers/clk/rockchip/clk-rk3588.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 906b849d00b3..070ecd9b92f2 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1471,7 +1471,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, RK3588_CLKGATE_CON(34), 6, GFLAGS), - GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_root", 0, + GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, RK3588_CLKGATE_CON(34), 7, GFLAGS), GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, RK3588_CLKGATE_CON(34), 8, GFLAGS), @@ -1485,15 +1485,15 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(33), 0, GFLAGS), GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, RK3588_CLKGATE_CON(33), 1, GFLAGS), - GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_pcie_root", 0, + GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, RK3588_CLKGATE_CON(33), 2, GFLAGS), - GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_pcie_root", 0, + GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, RK3588_CLKGATE_CON(33), 3, GFLAGS), - GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_pcie_root", 0, + GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, RK3588_CLKGATE_CON(33), 4, GFLAGS), - GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_pcie_root", 0, + GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, RK3588_CLKGATE_CON(33), 5, GFLAGS), - GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_pcie_root", 0, + GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, RK3588_CLKGATE_CON(33), 6, GFLAGS), GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, RK3588_CLKGATE_CON(33), 7, GFLAGS), @@ -1546,9 +1546,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(32), 7, GFLAGS), GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, RK3588_CLKGATE_CON(32), 8, GFLAGS), - GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php_root", 0, + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(32), 10, GFLAGS), - GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_php_root", 0, + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(32), 11, GFLAGS), GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, RK3588_CLKGATE_CON(37), 4, GFLAGS), @@ -1556,11 +1556,11 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(37), 5, GFLAGS), GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, RK3588_CLKGATE_CON(37), 6, GFLAGS), - GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0, + GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(37), 7, GFLAGS), - GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0, + GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(37), 8, GFLAGS), - GATE(ACLK_SATA2, "aclk_sata2", "aclk_php_root", 0, + GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(37), 9, GFLAGS), COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, @@ -1571,7 +1571,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3588_CLKGATE_CON(37), 12, GFLAGS), - GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_php_root", 0, + GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(35), 7, GFLAGS), GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, RK3588_CLKGATE_CON(35), 8, GFLAGS),