From 34ba677dedf2dc1338bd5fcecc2169c5d32a75bd Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sun, 9 Mar 2025 17:03:04 +0800
Subject: [PATCH] PCI: rockchip: dw-ep: Support setting link_gen

Change-Id: I1b93b04e45a39e93e774a2ade8a00865f1e6f5ed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
index 92e611618dc6..9ece92aa6519 100644
--- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <uapi/linux/rk-pcie-ep.h>
 
+#include "../../pci.h"
 #include "../rockchip-pcie-dma.h"
 #include "pcie-designware.h"
 #include "pcie-dw-dmatest.h"
@@ -322,6 +323,8 @@ static int rockchip_pcie_get_io_resource(struct platform_device *pdev,
 		return -ENODEV;
 	}
 
+	rockchip->pci.link_gen = of_pci_get_max_link_speed(np);
+
 	return 0;
 }