From 34d2e51fc4b1fa78c8b8a1de7d20b6ce197e48c6 Mon Sep 17 00:00:00 2001 From: Mauro Ribeiro Date: Wed, 19 Nov 2014 16:58:38 -0200 Subject: [PATCH] amlogic patch to support: 640x480, 1280x1024 and 1920x1200 Change-Id: Ied4e43e5cb17d24a5abd7d0736c45df74d507bea Signed-off-by: Dongjin Kim --- arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c | 274 +++++++++++++++++- arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h | 54 +++- arch/arm/mach-meson8b/include/mach/tvregs.h | 238 +++++++++++---- drivers/amlogic/display/vout/enc_clk_config.c | 39 ++- drivers/amlogic/display/vout/tvconf.c | 60 +++- drivers/amlogic/display/vout/tvmode.h | 3 + drivers/amlogic/display/vout/tvoutc.c | 3 + drivers/amlogic/hdmi/hdmi_tx/hdmi_tx.c | 3 + drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c | 6 +- drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_video.c | 22 ++ .../linux/amlogic/hdmi_tx/hdmi_info_global.h | 2 + include/linux/amlogic/vout/vinfo.h | 11 +- 12 files changed, 619 insertions(+), 96 deletions(-) diff --git a/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c b/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c index 99bfe0aadee9..b493f005c5f8 100755 --- a/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c +++ b/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c @@ -280,6 +280,38 @@ static irqreturn_t intr_handler(int irq, void *dev_instance) return IRQ_HANDLED; } +/* + * mode: 1 means Progressive; 0 means interlaced + */ +static void enc_vpu_bridge_reset(int mode) +{ + unsigned int wr_clk = 0; + + printk("%s[%d]\n", __func__, __LINE__); + wr_clk = (aml_read_reg32(P_VPU_HDMI_SETTING) & 0xf00) >> 8; + if(mode) { + aml_write_reg32(P_ENCP_VIDEO_EN, 0); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 0, 2); // [ 0] src_sel_enci: Disable ENCP output to HDMI + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 8, 4); // [ 0] src_sel_enci: Disable ENCP output to HDMI + mdelay(1); + aml_write_reg32(P_ENCP_VIDEO_EN, 1); + mdelay(1); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); + mdelay(1); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 2, 0, 2); // [ 0] src_sel_enci: Enable ENCP output to HDMI + } else { + aml_write_reg32(P_ENCI_VIDEO_EN, 0); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 0, 2); // [ 0] src_sel_enci: Disable ENCI output to HDMI + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 8, 4); // [ 0] src_sel_enci: Disable ENCP output to HDMI + mdelay(1); + aml_write_reg32(P_ENCI_VIDEO_EN, 1); + mdelay(1); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); + mdelay(1); + aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 0, 2); // [ 0] src_sel_enci: Enable ENCI output to HDMI + } +} + static void hdmi_tvenc1080i_set(Hdmi_tx_video_para_t* param) { unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; // Annie 01Sep2011: Change value from 3 to 2, due to video encoder path delay change. @@ -423,7 +455,6 @@ static void hdmi_tvenc1080i_set(Hdmi_tx_video_para_t* param) (0 <<12) // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2. ); aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 1, 1); // [ 1] src_sel_encp: Enable ENCP output to HDMI - } static void hdmi_tvenc480i_set(Hdmi_tx_video_para_t* param) @@ -599,7 +630,6 @@ static void hdmi_tvenc480i_set(Hdmi_tx_video_para_t* param) (1 <<12) // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2. ); aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI - } static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) @@ -621,6 +651,7 @@ static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) unsigned long vs_bline_evn, vs_eline_evn, vs_bline_odd, vs_eline_odd; unsigned long vso_begin_evn, vso_begin_odd; + if((param->VIC==HDMI_480p60)||(param->VIC==HDMI_480p60_16x9)){ INTERLACE_MODE = 0; PIXEL_REPEAT_VENC = 1; @@ -637,6 +668,22 @@ static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) SOF_LINES = 30; TOTAL_FRAMES = 4; } + else if(param->VIC==HDMI_640x480p60){ + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (640*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line. + ACTIVE_LINES = (480/(1+INTERLACE_MODE)); // Number of active lines per field. + LINES_F0 = 525; + LINES_F1 = 525; + FRONT_PORCH = 16; + HSYNC_PIXELS = 96; + BACK_PORCH = 48; + EOF_LINES = 10; + VSYNC_LINES = 2; + SOF_LINES = 33; + TOTAL_FRAMES = 4; + } else if((param->VIC==HDMI_576p50)||(param->VIC==HDMI_576p50_16x9)){ INTERLACE_MODE = 0; PIXEL_REPEAT_VENC = 1; @@ -685,6 +732,39 @@ static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) SOF_LINES = 20; TOTAL_FRAMES = 4; } + else if(param->VIC==HDMI_1280x1024){ + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line. + ACTIVE_LINES = (1024/(1+INTERLACE_MODE)); // Number of active lines per field. + LINES_F0 = 1066; + LINES_F1 = 1066; + FRONT_PORCH = 48; + HSYNC_PIXELS = 112; + BACK_PORCH = 248; + EOF_LINES = 1; + VSYNC_LINES = 3; + SOF_LINES = 38; + TOTAL_FRAMES = 4; + } + else if(param->VIC==HDMI_1920x1200) + { + INTERLACE_MODE =0; + PIXEL_REPEAT_VENC =0; + PIXEL_REPEAT_HDMI =0; + ACTIVE_PIXELS =(1920 *(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line. + ACTIVE_LINES =(1200/(1+INTERLACE_MODE)); // Number of active lines per field. + LINES_F0 =1235; + LINES_F1 =1235; + FRONT_PORCH =48; + HSYNC_PIXELS =32; + BACK_PORCH =80; + EOF_LINES =3; + VSYNC_LINES =6; + SOF_LINES =26; + TOTAL_FRAMES =4; + } else if(param->VIC==HDMI_1080p50){ INTERLACE_MODE =0; PIXEL_REPEAT_VENC =0; @@ -826,6 +906,9 @@ static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) (0 <<12) // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2. ); break; + case HDMI_640x480p60: + aml_write_reg32(P_VPU_HDMI_SETTING, 2); + break; case HDMI_720p60: case HDMI_720p50: // Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead. @@ -872,7 +955,7 @@ static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param) // Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead. aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 1, 1); // [ 1] src_sel_encp: Enable ENCP output to HDMI -} +} /* hdmi on/off @@ -1005,6 +1088,7 @@ void hdmi_hw_set_powermode(hdmitx_dev_t* hdmitx_device) int vic = hdmitx_device->cur_VIC; switch(vic) { + case HDMI_1280x1024: case HDMI_480i60: case HDMI_480i60_16x9: case HDMI_576p50: @@ -1233,7 +1317,7 @@ static void hdmi_hw_reset(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t *par if(new_reset_sequence_flag==0){ if(serial_reg_val==0){ if((param->VIC==HDMI_1080p30)||(param->VIC==HDMI_720p60)||(param->VIC==HDMI_1080i60) - ||(param->VIC==HDMI_1080p24)){ + ||(param->VIC==HDMI_1080p24)|| (param->VIC==HDMI_1280x1024) || (param->VIC==HDMI_640x480p60)){ hdmi_wr_reg(0x018, 0x22); } else{ @@ -1733,6 +1817,15 @@ static void hdmitx_set_pll(Hdmi_tx_video_para_t *param) case HDMI_1080p50: set_vmode_clk(VMODE_1080P); break; + case HDMI_640x480p60: + set_vmode_clk(VMODE_VGA); + break; + case HDMI_1280x1024: + set_vmode_clk(VMODE_SXGA); + break; + case HDMI_1920x1200: + set_vmode_clk(VMODE_1920x1200); + break; default: break; } @@ -1753,6 +1846,8 @@ static void hdmitx_set_phy(hdmitx_dev_t* hdmitx_device) aml_write_reg32(P_HHI_HDMI_PHY_CNTL1, 2); \ msleep(1) + aml_write_reg32(P_HHI_HDMI_PHY_CNTL1, 0); + msleep(1); RESET_HDMI_PHY(); RESET_HDMI_PHY(); RESET_HDMI_PHY(); @@ -1774,6 +1869,7 @@ static int hdmitx_set_dispmode(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t &&(param->VIC!=HDMI_1080p24) &&(param->VIC!=HDMI_1080p60)&&(param->VIC!=HDMI_1080p50) &&(param->VIC!=HDMI_720p60)&&(param->VIC!=HDMI_720p50) + &&(param->VIC!=HDMI_640x480p60) &&(param->VIC!=HDMI_1280x1024) &&(param->VIC!=HDMI_1920x1200) &&(param->VIC!=HDMI_4k2k_30)&&(param->VIC!=HDMI_4k2k_25)&&(param->VIC!=HDMI_4k2k_24)&&(param->VIC!=HDMI_4k2k_smpte_24) &&(param->VIC!=HDMI_1080i60)&&(param->VIC!=HDMI_1080i50)){ return -1; @@ -1800,8 +1896,6 @@ static int hdmitx_set_dispmode(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t hdmitx_device->cur_VIC = param->VIC; hdmi_tx_gate_pwr_ctrl(VID_EN, hdmitx_device); hdmi_hw_reset(hdmitx_device, param); - hdmitx_set_pll(param); - hdmitx_set_phy(hdmitx_device); if((param->VIC==HDMI_720p60)||(param->VIC==HDMI_720p50)|| (param->VIC==HDMI_1080i60)||(param->VIC==HDMI_1080i50)){ @@ -1829,19 +1923,36 @@ static int hdmitx_set_dispmode(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t // reset TX_SYS5_TX_SOFT_RESET_1/2 twice hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_1, 0xff); - hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x9f); + hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0xff); mdelay(5); hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_1, 0x00); - hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x60); + hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x00); mdelay(5); hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_1, 0xff); - hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x9f); + hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0xff); mdelay(5); hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_1, 0x00); - hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x60); + hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x00); mdelay(5); + hdmitx_set_pll(param); + switch(param->VIC) { + case HDMI_480i60: + case HDMI_480i60_16x9: + case HDMI_576i50: + case HDMI_576i50_16x9: + case HDMI_480i60_16x9_rpt: + case HDMI_576i50_16x9_rpt: + enc_vpu_bridge_reset(0); + break; + default: + enc_vpu_bridge_reset(1); + break; + } + + hdmitx_set_phy(hdmitx_device); + return 0; } @@ -2006,6 +2117,130 @@ static void set_hdmi_audio_source(unsigned int src) } } /* set_hdmi_audio_source */ +static void hdmitx_set_aud_pkt_type(audio_type_t type) +{ + // TX_AUDIO_CONTROL [5:4] + // 0: Audio sample packet (HB0 = 0x02) + // 1: One bit audio packet (HB0 = 0x07) + // 2: HBR Audio packet (HB0 = 0x09) + // 3: DST Audio packet (HB0 = 0x08) + switch(type) { + case CT_MAT: + hdmi_set_reg_bits(TX_AUDIO_CONTROL, 0x2, 4, 2); + break; + case CT_ONE_BIT_AUDIO: + hdmi_set_reg_bits(TX_AUDIO_CONTROL, 0x1, 4, 2); + break; + case CT_DST: + hdmi_set_reg_bits(TX_AUDIO_CONTROL, 0x3, 4, 2); + break; + default: + hdmi_set_reg_bits(TX_AUDIO_CONTROL, 0x0, 4, 2); + break; + } +} + +static Cts_conf_tab cts_table_192k[] = { + {24576, 27000, 27000}, + {24576, 54000, 54000}, + {24576, 108000, 108000}, + {24576, 74250, 74250}, + {24576, 148500, 148500}, + {24576, 297000, 247500}, +}; + +static unsigned int get_cts(unsigned int clk) +{ + int i; + + for(i = 0; i < ARRAY_SIZE(cts_table_192k); i++) { + if(clk == cts_table_192k[i].tmds_clk) + return cts_table_192k[i].fixed_cts; + } + + return 0; +} + +static Vic_attr_map vic_attr_map_table[] = { + {HDMI_640x480p60, 27000 }, + {HDMI_480p60, 27000 }, + {HDMI_480p60_16x9, 27000 }, + {HDMI_720p60, 74250 }, + {HDMI_1080i60, 74250 }, + {HDMI_480i60, 27000 }, + {HDMI_480i60_16x9, 27000 }, + {HDMI_480i60_16x9_rpt, 54000 }, + {HDMI_1440x480p60, 27000 }, + {HDMI_1440x480p60_16x9, 27000 }, + {HDMI_1080p60, 148500}, + {HDMI_576p50, 27000 }, + {HDMI_576p50_16x9, 27000 }, + {HDMI_720p50, 74250 }, + {HDMI_1280x1024, 108000}, + {HDMI_1080i50, 74250 }, + {HDMI_576i50, 27000 }, + {HDMI_576i50_16x9, 27000 }, + {HDMI_576i50_16x9_rpt, 54000 }, + {HDMI_1080p50, 148500}, + {HDMI_1080p24, 74250 }, + {HDMI_1080p25, 74250 }, + {HDMI_1080p30, 74250 }, + {HDMI_480p60_16x9_rpt, 108000}, + {HDMI_576p50_16x9_rpt, 108000}, + {HDMI_4k2k_24, 297000}, + {HDMI_4k2k_25, 297000}, + {HDMI_4k2k_30, 297000}, + {HDMI_4k2k_smpte_24, 297000}, +}; + +static unsigned int vic_map_clk(HDMI_Video_Codes_t vic) +{ + int i; + + for(i = 0; i < ARRAY_SIZE(vic_attr_map_table); i++) { + if(vic == vic_attr_map_table[i].VIC) + return vic_attr_map_table[i].tmds_clk; + } + + return 0; +} + +static void hdmitx_set_aud_cts(audio_type_t type, Hdmi_tx_audio_cts_t cts_mode, HDMI_Video_Codes_t vic) +{ + unsigned int cts_val = 0; + + switch(type) { + case CT_MAT: + if(cts_mode == AUD_CTS_FIXED) { + unsigned int clk = vic_map_clk(vic); + if(clk) { + cts_val = get_cts(clk); + if(!cts_val) + hdmi_print(ERR, AUD "not find cts\n"); + } + else { + hdmi_print(ERR, AUD "not find tmds clk\n"); + } + } + if(cts_mode == AUD_CTS_CALC) { + // TODO + } + break; + default: + hdmi_wr_reg(TX_SYS0_ACR_CTS_0, 0); //audio_CTS & 0xff); + hdmi_wr_reg(TX_SYS0_ACR_CTS_1, 0); //(audio_CTS>>8) & 0xff); + hdmi_wr_reg(TX_SYS0_ACR_CTS_2, 1 << 5); // set bit[5] force_arc_stable to 1 + break; + } + + if(cts_mode == AUD_CTS_FIXED) { + hdmi_wr_reg(TX_SYS0_ACR_CTS_0, cts_val & 0xff); + hdmi_wr_reg(TX_SYS0_ACR_CTS_1, (cts_val >> 8) & 0xff); + hdmi_wr_reg(TX_SYS0_ACR_CTS_2, ((cts_val >> 16) & 0xff) | (1 << 4)); + hdmi_print(IMP, AUD "type: %d CTS Mode: %d VIC: %d CTS: %d\n", type, cts_mode, vic, cts_val); + } +} + static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio_para_t* audio_param) { unsigned int audio_N_para = 6272; @@ -2038,6 +2273,7 @@ static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio //TMDS Clock:27MHz case HDMI_480p60: case HDMI_480p60_16x9: + case HDMI_640x480p60: case HDMI_576p50: case HDMI_576p50_16x9: case HDMI_480i60: @@ -2074,6 +2310,7 @@ static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio //TMDS Clock:74.176MHz case HDMI_720p60: case HDMI_720p50: + case HDMI_1280x1024: case HDMI_1080i60: case HDMI_1080i50: case HDMI_1080p30: @@ -2108,6 +2345,7 @@ static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio //TMDS Clock:148.5MHz case HDMI_1080p50: case HDMI_1080p60: + case HDMI_1920x1200: switch(audio_param->sample_rate) { case FS_32K: @@ -2145,12 +2383,21 @@ static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio audio_N_para = 6272 * 2; break; case FS_48K: - audio_N_para = 6144 * 2; + audio_N_para = 6144 * 2; + if((hdmitx_device->cur_VIC == HDMI_1080p24) || + (hdmitx_device->cur_VIC == HDMI_480p60) || + (hdmitx_device->cur_VIC == HDMI_480p60_16x9) || + (hdmitx_device->cur_VIC == HDMI_480i60) || + (hdmitx_device->cur_VIC == HDMI_480i60_16x9) ){ + audio_N_para = 6144 * 3; + } break; default: break; } + hdmitx_set_aud_pkt_type(audio_param->type); + //TODO. Different audio type, maybe have different settings switch(audio_param->type){ case CT_PCM: @@ -2208,6 +2455,11 @@ static int hdmitx_set_audmode(struct hdmi_tx_dev_s* hdmitx_device, Hdmi_tx_audio hdmi_wr_reg(TX_AUDIO_FORMAT, (hdmi_rd_reg(TX_AUDIO_FORMAT) & 0xfe)); // clear bit0, use channel status bit from input data } + if(audio_param->type == CT_MAT) + hdmitx_set_aud_cts(audio_param->type, AUD_CTS_FIXED, hdmitx_device->cur_VIC); + else + hdmitx_set_aud_cts(audio_param->type, AUD_CTS_AUTO, hdmitx_device->cur_VIC); + //todo hdmitx_special_handler_audio(hdmitx_device); return 0; diff --git a/arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h b/arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h index 204eb88fe089..14a785d52029 100644 --- a/arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h +++ b/arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h @@ -181,6 +181,56 @@ static reg_t hdmi_tvenc_regs_720p50[] = { {0,0} }; +static reg_t hdmi_tvenc_regs_640x480p60[] = { + //{ENCP_VIDEO_MODE, 0x00004040}, + //{ENCP_DE_H_BEGIN, 0x00000112}, + //{ENCP_DE_H_END, 0x00000612}, + //{ENCP_DE_V_BEGIN_EVEN, 0x00000029}, + //{ENCP_DE_V_END_EVEN, 0x00000429}, + //{ENCP_DVI_HSO_BEGIN, 0x00000052}, + //{ENCP_DVI_HSO_END, 0x000000c2}, + //{ENCP_DVI_VSO_BLINE_EVN, 0x00000000}, + //{ENCP_DVI_VSO_ELINE_EVN, 0x00000003}, + //{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052}, + //{ENCP_DVI_VSO_END_EVN, 0x00000052}, + //{VENC_DVI_SETTING_MORE, 0x00000000}, + //{VENC_DVI_SETTING, 0x0000809d}, + {0,0} +}; + +static reg_t hdmi_tvenc_regs_1280x1024x60[] = { + //{ENCP_VIDEO_MODE, 0x00004040}, + //{ENCP_DE_H_BEGIN, 0x00000112}, + //{ENCP_DE_H_END, 0x00000612}, + //{ENCP_DE_V_BEGIN_EVEN, 0x00000029}, + //{ENCP_DE_V_END_EVEN, 0x00000429}, + //{ENCP_DVI_HSO_BEGIN, 0x00000052}, + //{ENCP_DVI_HSO_END, 0x000000c2}, + //{ENCP_DVI_VSO_BLINE_EVN, 0x00000000}, + //{ENCP_DVI_VSO_ELINE_EVN, 0x00000003}, + //{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052}, + //{ENCP_DVI_VSO_END_EVN, 0x00000052}, + //{VENC_DVI_SETTING_MORE, 0x00000000}, + //{VENC_DVI_SETTING, 0x0000809d}, + {0,0} +}; + +static reg_t hdmi_tvenc_regs_1920x1200[] = {//60hz + //{ENCP_VIDEO_MODE, 0x00004040}, + //{ENCP_DE_H_BEGIN, 0x00000112}, + //{ENCP_DE_H_END, 0x00000612}, + //{ENCP_DE_V_BEGIN_EVEN, 0x00000029}, + //{ENCP_DE_V_END_EVEN, 0x00000429}, + //{ENCP_DVI_HSO_BEGIN, 0x00000052}, + //{ENCP_DVI_HSO_END, 0x000000c2}, + //{ENCP_DVI_VSO_BLINE_EVN, 0x00000000}, + //{ENCP_DVI_VSO_ELINE_EVN, 0x00000003}, + //{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052}, + //{ENCP_DVI_VSO_END_EVN, 0x00000052}, + //{VENC_DVI_SETTING_MORE, 0x00000000}, + //{VENC_DVI_SETTING, 0x0000809d}, + {0,0} +}; static reg_t hdmi_tvenc_regs_1080p50[] = { {ENCP_VIDEO_MODE, 0x00004040}, {ENCP_DE_H_BEGIN, 0x00000112}, @@ -205,7 +255,7 @@ typedef struct hdmi_tvenc_config_ }hdmi_tvenc_config_t; static const hdmi_tvenc_config_t hdmi_tvenc_configs[] = { - {HDMI_640x480p60 , NULL }, + {HDMI_640x480p60 , hdmi_tvenc_regs_640x480p60}, {HDMI_480p60, hdmi_tvenc_regs_480p}, {HDMI_480p60_16x9, hdmi_tvenc_regs_480p}, {HDMI_720p60, hdmi_tvenc_regs_720p}, @@ -218,6 +268,8 @@ static const hdmi_tvenc_config_t hdmi_tvenc_configs[] = { {HDMI_576p50, hdmi_tvenc_regs_576p}, {HDMI_576p50_16x9, hdmi_tvenc_regs_576p}, {HDMI_720p50, hdmi_tvenc_regs_720p50}, + {HDMI_1280x1024, hdmi_tvenc_regs_1280x1024x60}, + {HDMI_1920x1200, hdmi_tvenc_regs_1920x1200}, {HDMI_1080i50, hdmi_tvenc_regs_1080i50}, {HDMI_576i50, hdmi_tvenc_regs_576i}, {HDMI_576i50_16x9, hdmi_tvenc_regs_576i}, diff --git a/arch/arm/mach-meson8b/include/mach/tvregs.h b/arch/arm/mach-meson8b/include/mach/tvregs.h index caad3f875be8..5773720ac9ba 100755 --- a/arch/arm/mach-meson8b/include/mach/tvregs.h +++ b/arch/arm/mach-meson8b/include/mach/tvregs.h @@ -1129,78 +1129,66 @@ static const reg_t tvregs_4k2k_smpte[] = { //24hz {MREG_END_MARKER, 0 }, }; -static const reg_t tvregs_vga_640x480[] = { // 25.17mhz 800 *525 - {P_VENC_VDAC_SETTING, 0xff, }, - {P_HHI_VID_CLK_CNTL, 0x0, }, - {P_HHI_VID_PLL_CNTL, 0x2001042d,}, - {P_HHI_VID_PLL_CNTL2, 0x814d3928,}, - {P_HHI_VID_PLL_CNTL3, 0x6b425012, }, - {P_HHI_VID_PLL_CNTL4, 0x110}, - {P_HHI_VID_PLL_CNTL, 0x0001042a,},//50 +static const reg_t tvregs_vga_640x480[] = { + //{P_VENC_VDAC_SETTING, 0xff, }, + //{P_HHI_VID_CLK_CNTL, 0x0, }, + //{P_HHI_VID_PLL_CNTL2, 0x814d3928 }, + //{P_HHI_VID_PLL_CNTL3, 0x6b425012 }, + //{P_HHI_VID_PLL_CNTL4, 0x110 }, + //{P_HHI_VID_PLL_CNTL, 0x0001043e,}, + //{P_HHI_VID_DIVIDER_CNTL, 0x00011943,}, + //{P_HHI_VID_CLK_DIV, 0x100}, + //{P_HHI_VID_CLK_CNTL, 0x80000, }, + //{P_HHI_VID_CLK_CNTL, 0x88001, }, + //{P_HHI_VID_CLK_CNTL, 0x80003, }, + //{P_HHI_VIID_CLK_DIV, 0x00000101,}, - {P_HHI_VID_DIVIDER_CNTL, 0x00011943,}, - {P_HHI_VID_CLK_DIV, 0x100}, - {P_HHI_VID_CLK_CNTL, 0x80000,}, - {P_HHI_VID_CLK_CNTL, 0x88001,}, - {P_HHI_VID_CLK_CNTL, 0x80003,}, - {P_HHI_VIID_CLK_DIV, 0x00000101,}, {P_ENCP_VIDEO_FILT_CTRL, 0x1052,}, - //{P_HHI_VID_CLK_DIV, 0x01000100,}, - {P_ENCP_VIDEO_FILT_CTRL, 0x2052,}, - {P_VENC_DVI_SETTING, 0x21, }, - {P_ENCP_VIDEO_MODE, 0, }, - {P_ENCP_VIDEO_MODE_ADV, 0x009, }, - {P_ENCP_VIDEO_YFP1_HTIME, 244, }, - {P_ENCP_VIDEO_YFP2_HTIME, 1630, }, - {P_ENCP_VIDEO_YC_DLY, 0, }, - {P_ENCP_VIDEO_MAX_PXCNT, 1599, }, - {P_ENCP_VIDEO_MAX_LNCNT, 525, }, - {P_ENCP_VIDEO_HSPULS_BEGIN, 0x60, }, - {P_ENCP_VIDEO_HSPULS_END, 0xa0, }, + {P_VENC_DVI_SETTING, 0x0001,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018,}, + {P_ENCP_VIDEO_YFP1_HTIME, 140, }, + {P_ENCP_VIDEO_YFP2_HTIME, 2060, }, + {P_ENCP_VIDEO_MAX_PXCNT, 799, }, + {P_ENCP_VIDEO_HSPULS_BEGIN, 0, }, + {P_ENCP_VIDEO_HSPULS_END, 96, }, {P_ENCP_VIDEO_HSPULS_SWITCH, 88, }, {P_ENCP_VIDEO_VSPULS_BEGIN, 0, }, - {P_ENCP_VIDEO_VSPULS_END, 1589 }, + {P_ENCP_VIDEO_VSPULS_END, 0, }, {P_ENCP_VIDEO_VSPULS_BLINE, 0, }, - {P_ENCP_VIDEO_VSPULS_ELINE, 5, }, - {P_ENCP_VIDEO_HAVON_BEGIN, 153, }, - {P_ENCP_VIDEO_HAVON_END, 1433, }, - {P_ENCP_VIDEO_VAVON_BLINE, 59, }, - {P_ENCP_VIDEO_VAVON_ELINE, 540, }, - {P_ENCP_VIDEO_SYNC_MODE, 0x07, }, - {P_VENC_VIDEO_PROG_MODE, 0x100, }, - {P_VENC_VIDEO_EXSRC, 0x0, }, - {P_ENCP_VIDEO_HSO_BEGIN, 0x3, }, - {P_ENCP_VIDEO_HSO_END, 0x5, }, - {P_ENCP_VIDEO_VSO_BEGIN, 0x3, }, - {P_ENCP_VIDEO_VSO_END, 0x5, }, + {P_ENCP_VIDEO_VSPULS_ELINE, 2, }, + {P_ENCP_VIDEO_HAVON_BEGIN, 145, }, + {P_ENCP_VIDEO_HAVON_END, 784, }, + {P_ENCP_VIDEO_VAVON_BLINE, 35, }, + {P_ENCP_VIDEO_VAVON_ELINE, 515, }, + {P_ENCP_VIDEO_HSO_BEGIN, 0, }, + {P_ENCP_VIDEO_HSO_END, 96, }, + {P_ENCP_VIDEO_VSO_BEGIN, 0, }, + {P_ENCP_VIDEO_VSO_END, 0, }, {P_ENCP_VIDEO_VSO_BLINE, 0, }, - {P_ENCP_VIDEO_SY_VAL, 8, }, - {P_ENCP_VIDEO_SY2_VAL, 0x1d8, }, + {P_ENCP_VIDEO_VSO_ELINE, 2, }, + {P_ENCP_VIDEO_MAX_LNCNT, 524, }, + {P_VPU_VIU_VENC_MUX_CTRL, 0x000a,}, //New Add. If not set, when system boots up, switch panel to HDMI 1080P, nothing on TV. + {P_VENC_VIDEO_PROG_MODE, 0x100, }, {P_VENC_SYNC_ROUTE, 0, }, {P_VENC_INTCTRL, 0x200, }, - {P_ENCP_VFIFO2VD_CTL, 0, }, - {P_VENC_VDAC_SETTING, 0, }, - ///////////////////////////// - {P_ENCP_VIDEO_RGB_CTRL, 0,}, - {P_VENC_UPSAMPLE_CTRL0, 0xc061,}, - {P_VENC_UPSAMPLE_CTRL1, 0xd061,}, - {P_VENC_UPSAMPLE_CTRL2, 0xe061,}, - {P_VENC_VDAC_DACSEL0, 0xf003,}, - {P_VENC_VDAC_DACSEL1, 0xf003,}, - {P_VENC_VDAC_DACSEL2, 0xf003,}, - {P_VENC_VDAC_DACSEL3, 0xf003,}, - {P_VENC_VDAC_DACSEL4, 0xf003,}, - {P_VENC_VDAC_DACSEL5, 0xf003,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x000a,}, - {P_VENC_VDAC_FIFO_CTRL, 0x1fc0,}, - {P_ENCP_DACSEL_0, 0x0543,}, - {P_ENCP_DACSEL_1, 0x0000,}, + {P_ENCP_VFIFO2VD_CTL, 0,}, - {P_ENCI_VIDEO_EN, 0 }, - {P_ENCP_VIDEO_EN, 1 }, - {MREG_END_MARKER, 0 } -///////////////////////////////////// + {P_VENC_VDAC_SETTING, 0, }, + {P_VENC_VDAC_DACSEL0, 0x0001,}, + {P_VENC_VDAC_DACSEL1, 0x0001,}, + {P_VENC_VDAC_DACSEL2, 0x0001,}, + {P_VENC_VDAC_DACSEL3, 0x0001,}, + {P_VENC_VDAC_DACSEL4, 0x0001,}, + {P_VENC_VDAC_DACSEL5, 0x0001,}, + {P_VENC_VDAC_FIFO_CTRL, 0x1000,}, + {P_ENCP_DACSEL_0, 0x0543,}, + {P_ENCP_DACSEL_1, 0x0054,}, + {P_ENCI_VIDEO_EN, 0, }, + {P_ENCP_VIDEO_EN, 1, }, + {MREG_END_MARKER, 0 } }; + static const reg_t tvregs_svga_800x600[]={ //39.5mhz 1056 *628 {P_VENC_VDAC_SETTING, 0xff, }, {P_HHI_VID_CLK_CNTL, 0x0,}, @@ -1385,6 +1373,126 @@ static const reg_t tvregs_xga_1024x768[] = { }; +static const reg_t tvregs_sxga_1280x1024[] = { + {P_VENC_VDAC_SETTING, 0xff, }, + {P_HHI_VID_CLK_CNTL, 0x0, }, + {P_HHI_VID_PLL_CNTL2, 0x814d3928 }, + {P_HHI_VID_PLL_CNTL3, 0x6b425012 }, + {P_HHI_VID_PLL_CNTL4, 0x110 }, + {P_HHI_VID_PLL_CNTL, 0x0001043e,}, + {P_HHI_VID_DIVIDER_CNTL, 0x00011943,}, + {P_HHI_VID_CLK_DIV, 0x100}, + {P_HHI_VID_CLK_CNTL, 0x80000, }, + {P_HHI_VID_CLK_CNTL, 0x88001, }, + {P_HHI_VID_CLK_CNTL, 0x80003, }, + {P_HHI_VIID_CLK_DIV, 0x00000101,}, + + {P_ENCP_VIDEO_FILT_CTRL, 0x1052,}, + {P_VENC_DVI_SETTING, 0x0001,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018,}, + {P_ENCP_VIDEO_YFP1_HTIME, 140, }, + {P_ENCP_VIDEO_YFP2_HTIME, 2060, }, + {P_ENCP_VIDEO_MAX_PXCNT, 1687, }, + {P_ENCP_VIDEO_HSPULS_BEGIN, 1478, }, + {P_ENCP_VIDEO_HSPULS_END, 1590, }, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88, }, + {P_ENCP_VIDEO_VSPULS_BEGIN, 1478, }, + {P_ENCP_VIDEO_VSPULS_END, 1478, }, + {P_ENCP_VIDEO_VSPULS_BLINE, 1065, }, + {P_ENCP_VIDEO_VSPULS_ELINE, 2, }, + {P_ENCP_VIDEO_HAVON_BEGIN, 151, }, + {P_ENCP_VIDEO_HAVON_END, 1430, }, + {P_ENCP_VIDEO_VAVON_BLINE, 41, }, + {P_ENCP_VIDEO_VAVON_ELINE, 1065, }, + {P_ENCP_VIDEO_HSO_BEGIN, 1478, }, + {P_ENCP_VIDEO_HSO_END, 1590, }, + {P_ENCP_VIDEO_VSO_BEGIN, 1478, }, + {P_ENCP_VIDEO_VSO_END, 1478, }, + {P_ENCP_VIDEO_VSO_BLINE, 1065, }, + {P_ENCP_VIDEO_VSO_ELINE, 2, }, + {P_ENCP_VIDEO_MAX_LNCNT, 1065, }, + {P_VPU_VIU_VENC_MUX_CTRL, 0x000a,}, //New Add. If not set, when system boots up, switch panel to HDMI 1080P, nothing on TV. + {P_VENC_VIDEO_PROG_MODE, 0x100, }, + {P_VENC_SYNC_ROUTE, 0, }, + {P_VENC_INTCTRL, 0x200, }, + {P_ENCP_VFIFO2VD_CTL, 0,}, + + {P_VENC_VDAC_SETTING, 0, }, + {P_VENC_VDAC_DACSEL0, 0x0001,}, + {P_VENC_VDAC_DACSEL1, 0x0001,}, + {P_VENC_VDAC_DACSEL2, 0x0001,}, + {P_VENC_VDAC_DACSEL3, 0x0001,}, + {P_VENC_VDAC_DACSEL4, 0x0001,}, + {P_VENC_VDAC_DACSEL5, 0x0001,}, + {P_VENC_VDAC_FIFO_CTRL, 0x1000,}, + {P_ENCP_DACSEL_0, 0x0543,}, + {P_ENCP_DACSEL_1, 0x0054,}, + {P_ENCI_VIDEO_EN, 0, }, + {P_ENCP_VIDEO_EN, 1, }, + {MREG_END_MARKER, 0 } +}; + +static const reg_t tvregs_1920x1200[] = { + {P_VENC_VDAC_SETTING, 0xff, }, + {P_HHI_VID_CLK_CNTL, 0x0, }, + {P_HHI_VID_PLL_CNTL2, 0x814d3928 }, + {P_HHI_VID_PLL_CNTL3, 0x6b425012 }, + {P_HHI_VID_PLL_CNTL4, 0x110 }, + {P_HHI_VID_PLL_CNTL, 0x0001043e,}, + {P_HHI_VID_DIVIDER_CNTL, 0x00011943,}, + {P_HHI_VID_CLK_DIV, 0x100}, + {P_HHI_VID_CLK_CNTL, 0x80000, }, + {P_HHI_VID_CLK_CNTL, 0x88001, }, + {P_HHI_VID_CLK_CNTL, 0x80003, }, + {P_HHI_VIID_CLK_DIV, 0x00000101,}, + + {P_ENCP_VIDEO_FILT_CTRL, 0x1052,}, + {P_VENC_DVI_SETTING, 0x0001,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018,}, + {P_ENCP_VIDEO_YFP1_HTIME, 140, }, + {P_ENCP_VIDEO_YFP2_HTIME, 2060, }, + {P_ENCP_VIDEO_MAX_PXCNT, 2079, }, + {P_ENCP_VIDEO_HSPULS_BEGIN, 0, }, + {P_ENCP_VIDEO_HSPULS_END, 32, }, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88, }, + {P_ENCP_VIDEO_VSPULS_BEGIN, 0, }, + {P_ENCP_VIDEO_VSPULS_END, 0, }, + {P_ENCP_VIDEO_VSPULS_BLINE, 0, }, + {P_ENCP_VIDEO_VSPULS_ELINE, 6, }, + {P_ENCP_VIDEO_HAVON_BEGIN, 113, }, + {P_ENCP_VIDEO_HAVON_END, 2032, }, + {P_ENCP_VIDEO_VAVON_BLINE, 33, }, + {P_ENCP_VIDEO_VAVON_ELINE, 1233, }, + {P_ENCP_VIDEO_HSO_BEGIN, 0, }, + {P_ENCP_VIDEO_HSO_END, 32, }, + {P_ENCP_VIDEO_VSO_BEGIN, 0, }, + {P_ENCP_VIDEO_VSO_END, 0, }, + {P_ENCP_VIDEO_VSO_BLINE, 0, }, + {P_ENCP_VIDEO_VSO_ELINE, 6, }, + {P_ENCP_VIDEO_MAX_LNCNT, 1234, }, + {P_VPU_VIU_VENC_MUX_CTRL, 0x000a,}, //New Add. If not set, when system boots up, switch panel to HDMI 1080P, nothing on TV. + {P_VENC_VIDEO_PROG_MODE, 0x100, }, + {P_VENC_SYNC_ROUTE, 0, }, + {P_VENC_INTCTRL, 0x200, }, + {P_ENCP_VFIFO2VD_CTL, 0,}, + + {P_VENC_VDAC_SETTING, 0, }, + {P_VENC_VDAC_DACSEL0, 0x0001,}, + {P_VENC_VDAC_DACSEL1, 0x0001,}, + {P_VENC_VDAC_DACSEL2, 0x0001,}, + {P_VENC_VDAC_DACSEL3, 0x0001,}, + {P_VENC_VDAC_DACSEL4, 0x0001,}, + {P_VENC_VDAC_DACSEL5, 0x0001,}, + {P_VENC_VDAC_FIFO_CTRL, 0x1000,}, + {P_ENCP_DACSEL_0, 0x0543,}, + {P_ENCP_DACSEL_1, 0x0054,}, + {P_ENCI_VIDEO_EN, 0, }, + {P_ENCP_VIDEO_EN, 1, }, + {MREG_END_MARKER, 0 } +}; + /* The sequence of register tables items must match the enum define in tvmode.h */ static const reg_t *tvregsTab[] = { tvregs_480i, @@ -1408,9 +1516,11 @@ static const reg_t *tvregsTab[] = { tvregs_4k2k_25hz, tvregs_4k2k_24hz, tvregs_4k2k_smpte, + tvregs_1920x1200, tvregs_vga_640x480, tvregs_svga_800x600, - tvregs_xga_1024x768 + tvregs_xga_1024x768, + tvregs_sxga_1280x1024 }; static const tvinfo_t tvinfoTab[] = { @@ -1435,9 +1545,11 @@ static const tvinfo_t tvinfoTab[] = { {.xres = 3840, .yres = 2160, .id = "4k2k25hz"}, {.xres = 3840, .yres = 2160, .id = "4k2k24hz"}, {.xres = 4096, .yres = 2160, .id = "4k2ksmpte"}, + {.xres = 1920, .yres = 1200, .id = "1920x1200"}, {.xres = 640, .yres = 480, .id = "vga"}, {.xres = 800, .yres = 600, .id = "svga"}, {.xres = 1024, .yres = 768, .id = "xga"}, + {.xres = 1280, .yres = 1024, .id = "sxga"}, }; static inline void setreg(const reg_t *r) diff --git a/drivers/amlogic/display/vout/enc_clk_config.c b/drivers/amlogic/display/vout/enc_clk_config.c index 5f9ae886cdee..b3d1bf70332b 100755 --- a/drivers/amlogic/display/vout/enc_clk_config.c +++ b/drivers/amlogic/display/vout/enc_clk_config.c @@ -144,6 +144,15 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d); WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; + case 2014: + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c8cf55); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010429); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); + break; case 1488: aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8ce00); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); @@ -153,12 +162,32 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; + case 1540: + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c2ab); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000440); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000440); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); + break; case 1080: + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d); aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; case 1066: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a); + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042a); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042a); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; case 1058: WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422); @@ -512,9 +541,11 @@ static enc_clk_val_t setting_enc_clk_val[] = { {VMODE_1080I_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, {VMODE_1080P_50HZ, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, {VMODE_1080P_24HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_VGA, 1066, 3, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, - {VMODE_SVGA, 1058, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, - {VMODE_XGA, 1085, 1, 1, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, 1}, + {VMODE_VGA, 2014, 8, 1, 1, VIU_ENCP, 10, 4, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_SVGA, 1058, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, + {VMODE_XGA, 1085, 1, 1, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, 1}, + {VMODE_SXGA, 1080, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_1920x1200, 1540, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, #endif #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8 diff --git a/drivers/amlogic/display/vout/tvconf.c b/drivers/amlogic/display/vout/tvconf.c index f473e1fc50d1..7f92f435badf 100755 --- a/drivers/amlogic/display/vout/tvconf.c +++ b/drivers/amlogic/display/vout/tvconf.c @@ -74,7 +74,7 @@ static const tvmode_t vmode_tvmode_tab[] = { TVMODE_480I, TVMODE_480I_RPT, TVMODE_480CVBS, TVMODE_480P, TVMODE_480P_RPT, TVMODE_576I, TVMODE_576I_RPT, TVMODE_576CVBS, TVMODE_576P, TVMODE_576P_RPT, TVMODE_720P, TVMODE_1080I, TVMODE_1080P, TVMODE_720P_50HZ, TVMODE_1080I_50HZ, TVMODE_1080P_50HZ,TVMODE_1080P_24HZ, TVMODE_4K2K_30HZ, TVMODE_4K2K_25HZ, TVMODE_4K2K_24HZ, TVMODE_4K2K_SMPTE, - TVMODE_VGA, TVMODE_SVGA, TVMODE_XGA, TVMODE_SXGA + VMODE_1920x1200, TVMODE_VGA, TVMODE_SVGA, TVMODE_XGA, TVMODE_SXGA, TVMODE_WSXGA, TVMODE_FHDVGA, }; @@ -332,12 +332,24 @@ static const vinfo_t tv_info[] = .sync_duration_den = 1, .video_clk = 297000000, }, + { /* VMODE_1920x1200 */ + .name = "1920x1200", + .mode = VMODE_1920x1200, + .width = 1920, + .height = 1200, + .field_height = 1200, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 154000000, + }, { /* VMODE_vga */ .name = "vga", .mode = VMODE_VGA, .width = 640, .height = 480, - .field_height = 240, + .field_height = 480, .aspect_ratio_num = 4, .aspect_ratio_den = 3, .sync_duration_num = 60, @@ -380,6 +392,30 @@ static const vinfo_t tv_info[] = .sync_duration_den = 1, .video_clk = 108000000, }, + { /* VMODE_wsxga */ + .name = "wsxga", + .mode = VMODE_WSXGA, + .width = 1440, + .height = 900, + .field_height = 900, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 88750000, + }, + { /* VMODE_fhdvga */ + .name = "fhdvga", + .mode = VMODE_FHDVGA, + .width = 1920, + .height = 1080, + .field_height = 1080, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 148500000, + }, }; static const struct file_operations am_tv_fops = { @@ -422,7 +458,7 @@ tvmode_t vmode_to_tvmode(vmode_t mod) static int tv_set_current_vmode(vmode_t mod) { - if ((mod&VMODE_MODE_BIT_MASK)> VMODE_SXGA) + if ((mod&VMODE_MODE_BIT_MASK)> VMODE_FHDVGA) return -EINVAL; info->vinfo = &tv_info[mod & VMODE_MODE_BIT_MASK]; if(mod&VMODE_LOGO_BIT_MASK) return 0; @@ -555,7 +591,7 @@ static int create_tv_attr(disp_module_info_t* info) info->base_class=class_create(THIS_MODULE,info->name); if(IS_ERR(info->base_class)) { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"create tv display class fail\r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"create tv display class fail\n"); return -1 ; } //create class attr @@ -563,7 +599,7 @@ static int create_tv_attr(disp_module_info_t* info) { if ( class_create_file(info->base_class,tv_attr[i])) { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"create disp attribute %s fail\r\n",tv_attr[i]->attr.name); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"create disp attribute %s fail\n",tv_attr[i]->attr.name); } } sprintf(vdac_setting,"%x",get_current_vdac_setting()); @@ -578,7 +614,7 @@ static int __init tv_init_module(void) if (!info) { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"can't alloc display info struct\r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"can't alloc display info struct\n"); return -ENOMEM; } @@ -588,19 +624,19 @@ static int __init tv_init_module(void) ret=register_chrdev(0,info->name,&am_tv_fops); if(ret <0) { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register char dev tv error\r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register char dev tv error\n"); return ret ; } info->major=ret; _init_vout(); - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"major number %d for disp\r\n",ret); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"major number %d for disp\n",ret); if(vout_register_server(&tv_server)) { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register tv module server fail \r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register tv module server fail\n"); } else { - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register tv module server ok \r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"register tv module server ok\n"); } create_tv_attr(info); return 0; @@ -626,10 +662,10 @@ static __exit void tv_exit_module(void) } vout_unregister_server(&tv_server); - amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"exit tv module\r\n"); + amlog_mask_level(LOG_MASK_INIT,LOG_LEVEL_HIGH,"exit tv module\n"); } -#if ((defined CONFIG_ARCH_MESON8)) +#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) extern void cvbs_config_vdac(unsigned int flag, unsigned int cfg); static int __init vdac_config_bootargs_setup(char* line) diff --git a/drivers/amlogic/display/vout/tvmode.h b/drivers/amlogic/display/vout/tvmode.h index afaefe0ed2de..1b889a140587 100755 --- a/drivers/amlogic/display/vout/tvmode.h +++ b/drivers/amlogic/display/vout/tvmode.h @@ -47,10 +47,13 @@ typedef enum { TVMODE_4K2K_25HZ , TVMODE_4K2K_24HZ , TVMODE_4K2K_SMPTE , + TVMODE_1920x1200, TVMODE_VGA , TVMODE_SVGA, TVMODE_XGA, TVMODE_SXGA, + TVMODE_WSXGA, + TVMODE_FHDVGA, TVMODE_MAX } tvmode_t; diff --git a/drivers/amlogic/display/vout/tvoutc.c b/drivers/amlogic/display/vout/tvoutc.c index 4cffba02e225..257fefe28359 100755 --- a/drivers/amlogic/display/vout/tvoutc.c +++ b/drivers/amlogic/display/vout/tvoutc.c @@ -232,6 +232,9 @@ int tvoutc_setclk(tvmode_t mode) case TVMODE_1080I_50HZ: case TVMODE_1080P: case TVMODE_1080P_50HZ: + case TVMODE_SVGA: + case TVMODE_SXGA: + case TVMODE_1920x1200: setreg(&hd[xtal]); if(xtal == 1) { diff --git a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx.c b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx.c index 4eb0b9a1f151..116c98941faf 100755 --- a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx.c +++ b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx.c @@ -693,6 +693,9 @@ const char* disp_mode_t[]={ "4k2k25hz", "4k2k24hz", "4k2ksmpte", + "vga", + "sxga", + "1920x1200", NULL }; diff --git a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c index dd0aa17ddda2..6e36d10e3ba7 100755 --- a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c +++ b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c @@ -195,7 +195,7 @@ void Edid_DecodeStandardTiming(HDMI_TX_INFO_t * info, unsigned char * Data, unsi } } -static unsigned char Edid_TimingDescriptors[204]= //12x17 +static unsigned char Edid_TimingDescriptors[216]= //12x18 { //pixel clk --hsync active & blank -- vsync active & blank-- hsync/vsync off & wid -- Image size 0x8C,0x0A, 0xA0,0x14,0x51, 0xF0,0x16,0x00, 0x26,0x7c,0x43,0x00, //0x13,0x8e, //480i(4:3) @@ -208,6 +208,7 @@ static unsigned char Edid_TimingDescriptors[204]= //12x17 0x8C,0x0A, 0xD0,0x90,0x20, 0x40,0x31,0x20, 0x0c,0x40,0x55,0x00, // 0xc4,0x8e, //576p (16:9) 0x01,0x1D, 0x00,0x72,0x51, 0xD0,0x1E,0x20, 0x6e,0x28,0x55,0x00, // 0xc4,0x8e, //720p60(16:9) 0x01,0x1D, 0x00,0xBC,0x52, 0xD0,0x1E,0x20, 0xb8,0x28,0x55,0x40, // 0xc4,0x8e, //720p50 (16:9) + 0x01,0x1D, 0x00,0xBC,0x52, 0xD0,0x1E,0x20, 0xb8,0x28,0x55,0x40, // 0xc4,0x8e, //1280x1024 (4:3) 0x01,0x1D, 0x80,0x18,0x71, 0x1C,0x16,0x20, 0x58,0x2c,0x25,0x00, // 0xc4,0x8e, //1080i60 (16:9) 0x01,0x1D, 0x80,0xD0,0x72, 0x1C,0x16,0x20, 0x10,0x2c,0x25,0x80, // 0xc4,0x8e, //1080i50 (16:9) 0x02,0x3a, 0x80,0x18,0x71, 0x38,0x2d,0x40, 0x58,0x2c,0x45,0x00, // 0xc4,0x8e, //1080p60 (16:9) @@ -1298,6 +1299,9 @@ static dispmode_vic_t dispmode_VIC_tab[]= {"576p", HDMI_576p50_16x9}, {"720p50hz", HDMI_720p50}, {"720p", HDMI_720p60}, + {"vga", HDMI_640x480p60}, + {"sxga", HDMI_1280x1024}, + {"1920x1200", HDMI_1920x1200}, {"1080i50hz", HDMI_1080i50}, {"1080i", HDMI_1080i60}, {"1080p50hz", HDMI_1080p50}, diff --git a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_video.c b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_video.c index 70b1f2065fff..e811bc60cb97 100755 --- a/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_video.c +++ b/drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_video.c @@ -193,6 +193,28 @@ static Hdmi_tx_video_para_t hdmi_tx_video_params[] = .cc = CC_ITU709, .ss = SS_SCAN_UNDER, .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMI_1280x1024, + .color_prefer = COLOR_SPACE_RGB444, + .color_depth = COLOR_24BIT, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMI_1920x1200, + .color_prefer = COLOR_SPACE_RGB444, + .color_depth = COLOR_24BIT, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, }, { .VIC = HDMI_1080i50, diff --git a/include/linux/amlogic/hdmi_tx/hdmi_info_global.h b/include/linux/amlogic/hdmi_tx/hdmi_info_global.h index 415b8f1c50f8..d597762d302a 100644 --- a/include/linux/amlogic/hdmi_tx/hdmi_info_global.h +++ b/include/linux/amlogic/hdmi_tx/hdmi_info_global.h @@ -27,6 +27,8 @@ typedef enum HDMI_Video_Type_ { HDMI_1080p30, HDMI_480p60_16x9_rpt = 36, HDMI_576p50_16x9_rpt = 38, + HDMI_1280x1024 = 71, + HDMI_1920x1200 = 100, HDMI_4k2k_24 = 93, // CEA-861-F HDMI_4k2k_25, HDMI_4k2k_30, diff --git a/include/linux/amlogic/vout/vinfo.h b/include/linux/amlogic/vout/vinfo.h index e7d070af1855..2e2fa61baba4 100755 --- a/include/linux/amlogic/vout/vinfo.h +++ b/include/linux/amlogic/vout/vinfo.h @@ -49,14 +49,17 @@ typedef enum { VMODE_4K2K_25HZ , VMODE_4K2K_24HZ , VMODE_4K2K_SMPTE, + VMODE_1920x1200, VMODE_VGA, VMODE_SVGA, VMODE_XGA, VMODE_SXGA, - VMODE_LCD , - VMODE_LVDS_1080P, - VMODE_LVDS_1080P_50HZ, - VMODE_LVDS_768P, + VMODE_WSXGA, + VMODE_FHDVGA, + VMODE_LCD, + VMODE_LVDS_1080P, + VMODE_LVDS_1080P_50HZ, + VMODE_LVDS_768P, VMODE_MAX, VMODE_INIT_NULL, VMODE_MASK = 0xFF,