From 34f2cb9eaca3dcd5f6074e97eae9e7d78b8223f9 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Thu, 5 Nov 2020 16:53:48 +0800 Subject: [PATCH] clk/rockchip: rk3288: Add support for sclk_testout Change-Id: Ibd521712a6517300984db4199ac0164a499dc0f7 Signed-off-by: Wyon Bi Signed-off-by: Guochun Huang --- drivers/clk/rockchip/clk-rk3288.c | 12 ++++++++++++ include/dt-bindings/clock/rk3288-cru.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index e71d71039d65..238b80be230c 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -205,6 +205,12 @@ PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" }; +PNAME(mux_testout_src_p) = { "aclk_peri", "armclk", "aclk_vio0", "ddrphy", + "aclk_vcodec", "aclk_gpu", "sclk_rga", "aclk_cpu", + "xin24m", "xin27m", "xin32k", "clk_wifi", + "dclk_vop0", "dclk_vop1", "sclk_isp_jpe", + "sclk_isp" }; + PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m" }; PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; @@ -559,6 +565,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(2), 0, 6, DFLAGS, RK3288_CLKGATE_CON(2), 7, GFLAGS), + MUX(SCLK_TESTOUT_SRC, "sclk_testout_src", mux_testout_src_p, 0, + RK3288_MISC_CON, 8, 4, MFLAGS), + COMPOSITE_NOMUX(SCLK_TESTOUT, "sclk_testout", "sclk_testout_src", 0, + RK3288_CLKSEL_CON(2), 8, 5, DFLAGS, + RK3288_CLKGATE_CON(4), 15, GFLAGS), + COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, RK3288_CLKSEL_CON(24), 8, 8, DFLAGS, RK3288_CLKGATE_CON(2), 8, GFLAGS), diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 5d7c3522ee6e..d4988da4b2a0 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -100,6 +100,8 @@ #define SCLK_MAC_PLL 150 #define SCLK_MAC 151 #define SCLK_MACREF_OUT 152 +#define SCLK_TESTOUT_SRC 153 +#define SCLK_TESTOUT 154 #define DCLK_VOP0 190 #define DCLK_VOP1 191