From 3530c217374743d74ddcccd79bd5ffd6cb17339f Mon Sep 17 00:00:00 2001
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Date: Fri, 27 Aug 2021 19:43:25 +0800
Subject: [PATCH] arm64: dts: rockchip: add sata for rk3588

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I0b6a83bca3ce1809a5004e6ac1b34eed0729b0c8
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 15 +++++++++++
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 31 +++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 4062b033b0a1..bb8f679cfd30 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -119,6 +119,21 @@
 		status = "disabled";
 	};
 
+	sata1: sata@fe220000 {
+		compatible = "snps,dwc-ahci";
+		reg = <0 0xfe220000 0 0x1000>;
+		clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+			 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>;
+		clock-names = "sata", "pmalive", "rxoob", "ref";
+		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hostc";
+		phys = <&combphy1_ps PHY_TYPE_SATA>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x1>;
+		power-domains = <&power RK3588_PD_PHP>;
+		status = "disabled";
+	};
+
 	combphy1_ps: phy@fee10000 {
 		compatible = "rockchip,rk3588-naneng-combphy";
 		reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 25a02d9da0b1..bbc2be0e3d30 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/rk3588-cru.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/rk3588-power.h>
 
 / {
@@ -913,6 +914,36 @@
 		status = "disabled";
 	};
 
+	sata0: sata@fe210000 {
+		compatible = "snps,dwc-ahci";
+		reg = <0 0xfe210000 0 0x1000>;
+		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>;
+		clock-names = "sata", "pmalive", "rxoob", "ref";
+		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hostc";
+		phys = <&combphy0_ps PHY_TYPE_SATA>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x1>;
+		power-domains = <&power RK3588_PD_PHP>;
+		status = "disabled";
+	};
+
+	sata2: sata@fe230000 {
+		compatible = "snps,dwc-ahci";
+		reg = <0 0xfe230000 0 0x1000>;
+		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>;
+		clock-names = "sata", "pmalive", "rxoob", "ref";
+		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hostc";
+		phys = <&combphy2_psu PHY_TYPE_SATA>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x1>;
+		power-domains = <&power RK3588_PD_PHP>;
+		status = "disabled";
+	};
+
 	sdmmc: mmc@fe2c0000 {
 		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe2c0000 0x0 0x4000>;