diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c
index 1e3428854568..8be1980533fa 100644
--- a/drivers/soc/rockchip/rockchip_opp_select.c
+++ b/drivers/soc/rockchip/rockchip_opp_select.c
@@ -2399,7 +2399,7 @@ int rockchip_opp_config_clks(struct device *dev, struct opp_table *opp_table,
 	unsigned long *target = data;
 	int ret;
 
-	if (info->is_scmi_clk && !info->is_runtime_active)
+	if (rockchip_opp_is_use_pvtpll(info) && !info->is_runtime_active)
 		return 0;
 
 	ret = clk_bulk_prepare_enable(info->nclocks, info->clocks);
@@ -2480,7 +2480,7 @@ int rockchip_opp_check_rate_volt(struct device *dev, struct rockchip_opp_info *i
 		return ret;
 	}
 
-	if (info->is_scmi_clk && !info->is_runtime_active)
+	if (rockchip_opp_is_use_pvtpll(info) && !info->is_runtime_active)
 		is_set_clk = false;
 	if (info->data && info->data->set_read_margin && info->is_runtime_active)
 		is_set_rm = true;
diff --git a/include/soc/rockchip/rockchip_opp_select.h b/include/soc/rockchip/rockchip_opp_select.h
index e11c4cccd4bb..b54a4fee8165 100644
--- a/include/soc/rockchip/rockchip_opp_select.h
+++ b/include/soc/rockchip/rockchip_opp_select.h
@@ -44,6 +44,7 @@ struct volt_rm_table {
 struct rockchip_opp_data {
 	config_clks_t config_clks;
 	config_regulators_t config_regulators;
+	bool is_use_pvtpll;
 
 	int (*get_soc_info)(struct device *dev, struct device_node *np,
 			    int *bin, int *process);
@@ -143,6 +144,11 @@ struct rockchip_opp_info {
 	bool pvtpll_low_temp;
 };
 
+static inline bool rockchip_opp_is_use_pvtpll(struct rockchip_opp_info *info)
+{
+	return (info->is_scmi_clk || (info->data && info->data->is_use_pvtpll));
+}
+
 #if IS_ENABLED(CONFIG_ROCKCHIP_OPP)
 int rockchip_of_get_leakage(struct device *dev, char *lkg_name, int *leakage);
 int rockchip_nvmem_cell_read_u8(struct device_node *np, const char *cell_id,