diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index adfbc36fa531..b1badc459c06 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -529,83 +529,83 @@ PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_ static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(26), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(28), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); + RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); + RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(30), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(32), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(120), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(142), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(146), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(148), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(131), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(122), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(155), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(157), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(34), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(36), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(124), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(150), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(152), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); + RK3588_CLKSEL_CON(126), 0, 2, MFLAGS | CLK_MUX_ROUND_CLOSEST); static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, @@ -888,7 +888,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, RK3588_CLKGATE_CON(7), 14, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(29), 0, + RK3588_CLKSEL_CON(29), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(7), 15, GFLAGS, &rk3588_i2s2_2ch_fracmux), GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, @@ -900,7 +900,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(8), 1, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(31), 0, + RK3588_CLKSEL_CON(31), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(8), 2, GFLAGS, &rk3588_i2s3_2ch_fracmux), GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, @@ -918,7 +918,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, RK3588_CLKGATE_CON(7), 5, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(25), 0, + RK3588_CLKSEL_CON(25), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(7), 6, GFLAGS, &rk3588_i2s0_8ch_tx_fracmux), GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, @@ -928,7 +928,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(7), 8, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(27), 0, + RK3588_CLKSEL_CON(27), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(7), 9, GFLAGS, &rk3588_i2s0_8ch_rx_fracmux), GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, @@ -948,7 +948,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(33), 0, + RK3588_CLKSEL_CON(33), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(9), 0, GFLAGS, &rk3588_spdif0_fracmux), GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, @@ -960,7 +960,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(9), 3, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(35), 0, + RK3588_CLKSEL_CON(35), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(9), 4, GFLAGS, &rk3588_spdif1_fracmux), GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, @@ -1836,7 +1836,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(56), 11, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(119), 0, + RK3588_CLKSEL_CON(119), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(56), 12, GFLAGS, &rk3588_i2s4_8ch_tx_fracmux), GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, @@ -1845,7 +1845,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(56), 15, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(121), 0, + RK3588_CLKSEL_CON(121), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(57), 0, GFLAGS, &rk3588_i2s8_8ch_tx_fracmux), GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, @@ -1854,7 +1854,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(57), 3, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(123), 0, + RK3588_CLKSEL_CON(123), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(57), 4, GFLAGS, &rk3588_spdif2_dp0_fracmux), GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, @@ -1865,7 +1865,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(57), 8, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(125), 0, + RK3588_CLKSEL_CON(125), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(57), 9, GFLAGS, &rk3588_spdif5_dp1_fracmux), GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, @@ -1986,7 +1986,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(65), 5, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(156), 0, + RK3588_CLKSEL_CON(156), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(65), 6, GFLAGS, &rk3588_i2s10_8ch_rx_fracmux), GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, @@ -1995,7 +1995,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, RK3588_CLKGATE_CON(60), 1, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(130), 0, + RK3588_CLKSEL_CON(130), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(60), 2, GFLAGS, &rk3588_i2s7_8ch_rx_fracmux), GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, @@ -2004,7 +2004,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, RK3588_CLKGATE_CON(65), 1, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(154), 0, + RK3588_CLKSEL_CON(154), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(65), 2, GFLAGS, &rk3588_i2s9_8ch_rx_fracmux), GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, @@ -2013,7 +2013,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, RK3588_CLKGATE_CON(62), 6, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(141), 0, + RK3588_CLKSEL_CON(141), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(62), 7, GFLAGS, &rk3588_i2s5_8ch_tx_fracmux), GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, @@ -2022,7 +2022,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(62), 13, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(145), 0, + RK3588_CLKSEL_CON(145), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(62), 14, GFLAGS, &rk3588_i2s6_8ch_tx_fracmux), GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, @@ -2031,7 +2031,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(63), 0, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(147), 0, + RK3588_CLKSEL_CON(147), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(63), 1, GFLAGS, &rk3588_i2s6_8ch_rx_fracmux), GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, @@ -2042,7 +2042,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, RK3588_CLKGATE_CON(63), 5, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(149), 0, + RK3588_CLKSEL_CON(149), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(63), 6, GFLAGS, &rk3588_spdif3_fracmux), GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, @@ -2051,7 +2051,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(63), 9, GFLAGS), COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(151), 0, + RK3588_CLKSEL_CON(151), CLK_MUX_ROUND_CLOSEST, RK3588_CLKGATE_CON(63), 10, GFLAGS, &rk3588_spdif4_fracmux), GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, @@ -2190,7 +2190,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3588_PMU_CLKSEL_CON(6), 0, + RK3588_PMU_CLKSEL_CON(6), CLK_MUX_ROUND_CLOSEST, RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, &rk3588_i2s1_8ch_tx_fracmux), GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, @@ -2199,7 +2199,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3588_PMU_CLKSEL_CON(8), 0, + RK3588_PMU_CLKSEL_CON(8), CLK_MUX_ROUND_CLOSEST, RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, &rk3588_i2s1_8ch_rx_fracmux), GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index caaf7706a37d..d38553dfad26 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -94,6 +94,13 @@ static const struct rockchip_gpio_regs gpio_regs_v2 = { .version_id = 0x78, }; +static enum rockchip_pinctrl_type chip_type; + +static inline bool is_rk3506_bank4(struct rockchip_pin_bank *bank) +{ + return IS_ENABLED(CONFIG_CPU_RK3506) && chip_type == RK3506 && bank->bank_num == 4; +} + static inline void gpio_writel_v2(u32 val, void __iomem *reg) { writel((val & 0xffff) | 0xffff0000, reg); @@ -110,6 +117,14 @@ static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, { void __iomem *reg = bank->reg_base + offset; + if (is_rk3506_bank4(bank)) { + u32 tmp = value & 0x3f; + + value &= 0xffffffc0; + value |= (tmp >> 1) & 0x15; + value |= (tmp << 1) & 0x2a; + } + if (bank->gpio_type >= GPIO_TYPE_V2) gpio_writel_v2(value, reg); else @@ -127,6 +142,14 @@ static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, else value = readl(reg); + if (is_rk3506_bank4(bank)) { + u32 tmp = value & 0x3f; + + value &= 0xffffffc0; + value |= (tmp >> 1) & 0x15; + value |= (tmp << 1) & 0x2a; + } + return value; } @@ -137,6 +160,9 @@ static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, void __iomem *reg = bank->reg_base + offset; u32 data; + if (is_rk3506_bank4(bank) && bit < 6) + bit ^= 0x1; + if (bank->gpio_type >= GPIO_TYPE_V2) { if (value) data = BIT(bit % 16) | BIT(bit % 16 + 16); @@ -158,6 +184,9 @@ static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, void __iomem *reg = bank->reg_base + offset; u32 data; + if (is_rk3506_bank4(bank) && bit < 6) + bit ^= 0x1; + if (bank->gpio_type >= GPIO_TYPE_V2) { data = readl(bit >= 16 ? reg + 0x4 : reg); data >>= bit % 16; @@ -709,6 +738,9 @@ rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) int i, found = 0; info = pinctrl_dev_get_drvdata(pctldev); + if (IS_ENABLED(CONFIG_CPU_RK3506)) + chip_type = info->ctrl->type; + bank = info->ctrl->pin_banks; for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { if (bank->bank_num == id) {