From 35ec91bf3ac04d9405c8dcbecd6afca112f44980 Mon Sep 17 00:00:00 2001 From: William Wu Date: Sun, 28 Jun 2020 11:30:45 +0800 Subject: [PATCH] phy: rockchip-inno-combphy: remove combphy_u3_cp_test The combphy_u3_cp_test() is used for USB3 compliance test, and it depends on the cp_test of phy_ops which will be dropped later, so we remove combphy_u3_cp_test directly. As a side effect, we need to use io commands to set the USB3 enter compliance test mode instead of host_testmode for RK1808 USB3 combphy. Change-Id: Iac7d9a4c6b0d2a74c284586f5dcbb48925691a91 Signed-off-by: William Wu --- .../phy/rockchip/phy-rockchip-inno-combphy.c | 38 ------------------- 1 file changed, 38 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c index b6dd1b9b9e42..e29590b7d1d3 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c @@ -70,7 +70,6 @@ struct rockchip_combphy_grfcfg { struct rockchip_combphy_cfg { const struct rockchip_combphy_grfcfg grfcfg; - int (*combphy_u3_cp_test)(struct rockchip_combphy_priv *priv); int (*combphy_cfg)(struct rockchip_combphy_priv *priv); int (*combphy_low_power_ctrl)(struct rockchip_combphy_priv *priv, bool en); @@ -565,28 +564,6 @@ done: return 0; } -static int rockchip_combphy_u3_cp_test(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); - int ret = 0; - - /* - * When do USB3 compliance test, we may connect the oscilloscope - * front panel Aux Out to the DUT SSRX+, the Aux Out of the - * oscilloscope outputs a negative pulse whose width is between - * 300- 400 ns which may trigger some DUTs to change the CP test - * pattern. - * - * The Inno USB3 PHY disable the function to detect the negative - * pulse in SSRX+ by default, so we need to enable the function - * to toggle the CP test pattern before do USB3 compliance test. - */ - if (priv->cfg->combphy_u3_cp_test) - ret = priv->cfg->combphy_u3_cp_test(priv); - - return ret; -} - static int rockchip_combphy_set_mode(struct phy *phy, enum phy_mode mode) { struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); @@ -614,7 +591,6 @@ static const struct phy_ops rockchip_combphy_ops = { .power_on = rockchip_combphy_power_on, .power_off = rockchip_combphy_power_off, .set_mode = rockchip_combphy_set_mode, - .cp_test = rockchip_combphy_u3_cp_test, .owner = THIS_MODULE, }; @@ -745,19 +721,6 @@ static int rockchip_combphy_remove(struct platform_device *pdev) return 0; } -static int rk1808_combphy_u3_cp_test(struct rockchip_combphy_priv *priv) -{ - if (priv->phy_type != PHY_TYPE_USB3) { - dev_err(priv->dev, "failed to set cp test for phy type %d\n", - priv->phy_type); - return -EINVAL; - } - - writel(0x0c, priv->mmio + 0x4008); - - return 0; -} - static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv) { unsigned long rate; @@ -1050,7 +1013,6 @@ static const struct rockchip_combphy_cfg rk1808_combphy_cfgs = { .u3_port_disable = { 0x0434, 0, 0, 0, 1}, .u3_port_num = { 0x0434, 15, 12, 0, 1}, }, - .combphy_u3_cp_test = rk1808_combphy_u3_cp_test, .combphy_cfg = rk1808_combphy_cfg, .combphy_low_power_ctrl = rk1808_combphy_low_power_control, };