From 35fb7dced2aa131b339401876d234c658e583f34 Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Mon, 14 Jan 2019 17:21:31 +0900 Subject: [PATCH] ODROID-N2: vout: hdmitx: adjust hdmi timing and hpll over 2Gbps 2560x1440p60hz / 2560x1600p60hz Change-Id: I10240001b7c655b95f4db5d3fea8cb147d7495ab (cherry picked from commit d7df8c31c62f3960e15c8dfd1d5852aada7b27e5) --- .../vout/hdmitx/hdmi_common/hdmi_parameters.c | 4 ++-- .../media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c | 4 ++-- .../media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 10 +++++++++- .../media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 4 ++-- .../media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c | 15 +++++++++++++++ 5 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c index 4d85b5b69682..d85853088d43 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c @@ -1394,9 +1394,9 @@ static struct hdmi_format_para fmt_para_2560x1440p60_16x9 = { .timing = { .pixel_freq = 241500, .frac_freq = 241500, - .h_freq = 98700, + .h_freq = 88790, .v_freq = 60000, - .vsync_polarity = 0, + .vsync_polarity = 1, .hsync_polarity = 1, .h_active = 2560, .h_total = 2720, diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c index 38eab89a796c..2cad818b0ac4 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c @@ -700,8 +700,8 @@ static const struct reg_s tvregs_2560x1600p_60hz[] = { {P_ENCP_VIDEO_MAX_LNCNT, 1645,}, {P_ENCP_VIDEO_HAVON_BEGIN, 80,}, {P_ENCP_VIDEO_HAVON_END, 2639,}, - {P_ENCP_VIDEO_VAVON_BLINE, 38,}, - {P_ENCP_VIDEO_VAVON_ELINE, 1637,}, + {P_ENCP_VIDEO_VAVON_BLINE, 37,}, + {P_ENCP_VIDEO_VAVON_ELINE, 1636,}, {P_ENCP_VIDEO_HSO_BEGIN, 0,}, {P_ENCP_VIDEO_HSO_END, 32,}, {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 651c135dcdef..4fa5a798edbc 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1506,7 +1506,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) FRONT_PORCH = 48; HSYNC_PIXELS = 32; BACK_PORCH = 80; - EOF_LINES = 2; + EOF_LINES = 3; VSYNC_LINES = 6; SOF_LINES = 38; TOTAL_FRAMES = 4; @@ -2101,6 +2101,14 @@ do { \ else set_phy_by_mode(1); break; + /* consider HPLL over 2Gbps */ + case HDMI_2560x1600p60_8x5: + case HDMI_2560x1440p60_16x9: + if (hdev->para->cd == COLORDEPTH_24B) + set_phy_by_mode(2); + else + set_phy_by_mode(1); + break; case HDMI_1080p60: case HDMI_1080p50: if (hdev->flag_3dfp) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index c8068820d0f5..37c69ff8dd57 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -779,10 +779,10 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { 5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1}, {{HDMI_2560x1600p60_8x5, HDMI_VIC_END}, - 2685000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + 5405400, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, {{HDMI_2560x1440p60_16x9, HDMI_VIC_END}, - 2415000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + 4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, {{HDMI_2560x1080p60_64x27, HDMI_VIC_END}, 1855800, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 0cda696a4b3b..80c6ed0fcad1 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -193,6 +193,21 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); break; + case 4830000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004c9); + if (frac_rate) + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000); + else + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; case 4455000: hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9); if (frac_rate)