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ALSA: hda/cirrus: Correct the full scale volume set logic

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[ Upstream commit 08b613b9e2ba431db3bd15cb68ca72472a50ef5c ]

This patch corrects the full-scale volume setting logic. On certain
platforms, the full-scale volume bit is required. The current logic
mistakenly sets this bit and incorrectly clears reserved bit 0, causing
the headphone output to be muted.

Fixes: 342b6b610a ("ALSA: hda/cs8409: Fix Full Scale Volume setting for all variants")
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Link: https://patch.msgid.link/20250214210736.30814-1-vitalyr@opensource.cirrus.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Vitaly Rodionov
2025-02-14 21:07:28 +00:00
committed by Greg Kroah-Hartman
parent 904e746b2e
commit 36069c768f
3 changed files with 17 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
sound/pci/hda/patch_cs8409-tables.c
View File

@@ -121,7 +121,7 @@ static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
{ CS42L42_MIXER_CHA_VOL, 0x3F }, { CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F }, { CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3f }, { CS42L42_MIXER_ADC_VOL, 0x3f },
{ CS42L42_HP_CTL, 0x03 }, { CS42L42_HP_CTL, 0x0D },
{ CS42L42_MIC_DET_CTL1, 0xB6 }, { CS42L42_MIC_DET_CTL1, 0xB6 },
{ CS42L42_TIPSENSE_CTL, 0xC2 }, { CS42L42_TIPSENSE_CTL, 0xC2 },
{ CS42L42_HS_CLAMP_DISABLE, 0x01 }, { CS42L42_HS_CLAMP_DISABLE, 0x01 },
@@ -315,7 +315,7 @@ static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = {
{ CS42L42_ASP_TX_SZ_EN, 0x01 }, { CS42L42_ASP_TX_SZ_EN, 0x01 },
{ CS42L42_PWR_CTL1, 0x0A }, { CS42L42_PWR_CTL1, 0x0A },
{ CS42L42_PWR_CTL2, 0x84 }, { CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_HP_CTL, 0x03 }, { CS42L42_HP_CTL, 0x0D },
{ CS42L42_MIXER_CHA_VOL, 0x3F }, { CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F }, { CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3f }, { CS42L42_MIXER_ADC_VOL, 0x3f },
@@ -371,7 +371,7 @@ static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = {
{ CS42L42_ASP_TX_SZ_EN, 0x00 }, { CS42L42_ASP_TX_SZ_EN, 0x00 },
{ CS42L42_PWR_CTL1, 0x0E }, { CS42L42_PWR_CTL1, 0x0E },
{ CS42L42_PWR_CTL2, 0x84 }, { CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_HP_CTL, 0x01 }, { CS42L42_HP_CTL, 0x0D },
{ CS42L42_MIXER_CHA_VOL, 0x3F }, { CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F }, { CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3f }, { CS42L42_MIXER_ADC_VOL, 0x3f },

20
sound/pci/hda/patch_cs8409.c
View File

@@ -876,7 +876,7 @@ static void cs42l42_resume(struct sub_codec *cs42l42)
{ CS42L42_DET_INT_STATUS2, 0x00 }, { CS42L42_DET_INT_STATUS2, 0x00 },
{ CS42L42_TSRS_PLUG_STATUS, 0x00 }, { CS42L42_TSRS_PLUG_STATUS, 0x00 },
}; };
int fsv_old, fsv_new; unsigned int fsv;
/* Bring CS42L42 out of Reset */ /* Bring CS42L42 out of Reset */
spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
@@ -893,13 +893,15 @@ static void cs42l42_resume(struct sub_codec *cs42l42)
/* Clear interrupts, by reading interrupt status registers */ /* Clear interrupts, by reading interrupt status registers */
cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs)); cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL); fsv = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB) if (cs42l42->full_scale_vol) {
fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK; // Set the full scale volume bit
else fsv |= CS42L42_FULL_SCALE_VOL_MASK;
fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK; cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
if (fsv_new != fsv_old) }
cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new); // Unmute analog channels A and B
fsv = (fsv & ~CS42L42_ANA_MUTE_AB);
cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
/* we have to explicitly allow unsol event handling even during the /* we have to explicitly allow unsol event handling even during the
* resume phase so that the jack event is processed properly * resume phase so that the jack event is processed properly
@@ -921,7 +923,7 @@ static void cs42l42_suspend(struct sub_codec *cs42l42)
{ CS42L42_MIXER_CHA_VOL, 0x3F }, { CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3F }, { CS42L42_MIXER_ADC_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F }, { CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_HP_CTL, 0x0F }, { CS42L42_HP_CTL, 0x0D },
{ CS42L42_ASP_RX_DAI0_EN, 0x00 }, { CS42L42_ASP_RX_DAI0_EN, 0x00 },
{ CS42L42_ASP_CLK_CFG, 0x00 }, { CS42L42_ASP_CLK_CFG, 0x00 },
{ CS42L42_PWR_CTL1, 0xFE }, { CS42L42_PWR_CTL1, 0xFE },

5
sound/pci/hda/patch_cs8409.h
View File

@@ -230,9 +230,10 @@ enum cs8409_coefficient_index_registers {
#define CS42L42_PDN_TIMEOUT_US (250000) #define CS42L42_PDN_TIMEOUT_US (250000)
#define CS42L42_PDN_SLEEP_US (2000) #define CS42L42_PDN_SLEEP_US (2000)
#define CS42L42_INIT_TIMEOUT_MS (45) #define CS42L42_INIT_TIMEOUT_MS (45)
#define CS42L42_ANA_MUTE_AB (0x0C)
#define CS42L42_FULL_SCALE_VOL_MASK (2) #define CS42L42_FULL_SCALE_VOL_MASK (2)
#define CS42L42_FULL_SCALE_VOL_0DB (1) #define CS42L42_FULL_SCALE_VOL_0DB (0)
#define CS42L42_FULL_SCALE_VOL_MINUS6DB (0) #define CS42L42_FULL_SCALE_VOL_MINUS6DB (1)
/* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */ /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */