diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 946f18705e96..be1207d5d404 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -176,14 +176,14 @@
 		#size-cells = <0>;
 		status = "disabled";
 
-		usbphy0: usb-phy0 {
+		usbphy0: usb-phy@17c {
 			#phy-cells = <0>;
 			reg = <0x17c>;
 			clocks = <&cru SCLK_OTGPHY0>;
 			clock-names = "phyclk";
 		};
 
-		usbphy1: usb-phy1 {
+		usbphy1: usb-phy@188 {
 			#phy-cells = <0>;
 			reg = <0x188>;
 			clocks = <&cru SCLK_OTGPHY1>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 6399942f1840..7afcf1b42e88 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -151,14 +151,14 @@
 		#size-cells = <0>;
 		status = "disabled";
 
-		usbphy0: usb-phy0 {
+		usbphy0: usb-phy@10c {
 			#phy-cells = <0>;
 			reg = <0x10c>;
 			clocks = <&cru SCLK_OTGPHY0>;
 			clock-names = "phyclk";
 		};
 
-		usbphy1: usb-phy1 {
+		usbphy1: usb-phy@11c {
 			#phy-cells = <0>;
 			reg = <0x11c>;
 			clocks = <&cru SCLK_OTGPHY1>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4f48c5011982..dada333aa96d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -862,33 +862,36 @@
 			status = "disabled";
 		};
 
-		usbphy: phy {
+		usbphy: usbphy {
 			compatible = "rockchip,rk3288-usb-phy";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 
-			usbphy0: usb-phy0 {
+			usbphy0: usb-phy@320 {
 				#phy-cells = <0>;
 				reg = <0x320>;
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
+				#clock-cells = <0>;
 				resets = <&cru SRST_USBOTG_PHY>;
 				reset-names = "phy-reset";
 			};
 
-			usbphy1: usb-phy1 {
+			usbphy1: usb-phy@334 {
 				#phy-cells = <0>;
 				reg = <0x334>;
 				clocks = <&cru SCLK_OTGPHY1>;
 				clock-names = "phyclk";
+				#clock-cells = <0>;
 			};
 
-			usbphy2: usb-phy2 {
+			usbphy2: usb-phy@348 {
 				#phy-cells = <0>;
 				reg = <0x348>;
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
+				#clock-cells = <0>;
 				resets = <&cru SRST_USBHOST1_PHY>;
 				reset-names = "phy-reset";
 			};