From 3705226ed074f8a7bc0d87ad70a57fbdb9ef056d Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Thu, 13 May 2021 05:54:15 +0900 Subject: [PATCH] ODROID-M1: arch/arm64: add new board Hardkernel's ODROID-M1 Signed-off-by: Dongjin Kim Signed-off-by: Deokgyu Yang Signed-off-by: Steve Jeong Change-Id: Ifbcc33e8e5c3064b3f4cbd3f6a92224346c4f4b3 ODROID-M1: arm64/dts: change i2c2 pinctrl. - Changed the I2C-2 default pinctrl to i2c2m1_xfer. Signed-off-by: Luke Go Change-Id: Id234f0d73100e98502b86f91b455cacc2fc6847f --- arch/arm64/Kconfig.platforms | 10 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 174 ++++++++++++++++++ .../boot/dts/rockchip/rk3568-odroid.dtsi | 118 ++++++++++++ 4 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 2b2f34e571e6..65f6863fef9c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -353,4 +353,14 @@ config ARCH_ZYNQMP help This enables support for Xilinx ZynqMP Family +config ARCH_ROCKCHIP_ODROID_COMMON + bool + +config ARCH_ROCKCHIP_ODROIDM1 + bool "Hardkernel's ODROID-M1 Single Board Computer" + select ARCH_ROCKCHIP_ODROID_COMMON + help + This enables support for the board ODROID-M1 of Hardkernel + which is based on ARMv8 SoC of Rockchip, Inc. + endmenu # "Platform selection" diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d1c81766d08a..4f43f03cbac1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -414,3 +414,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb-v14.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb-v14-dual-cam.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb1-v12.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb1-v12-fastboot-emmc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts new file mode 100644 index 000000000000..9097f5e259f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-odroid.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Hardkernel ODROID-M1"; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + i2c0 = &i2c3; + i2c3 = &i2c0; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A */ + "", "", "", "", "", "", "", "", + /* GPIO0_B */ + "", "", "", + "PIN_28", /* GPIO0_B3 */ + "PIN_27", /* GPIO0_B4 */ + "PIN_33", /* GPIO0_B5 */ + "PIN_7", /* GPIO0_B6 */ + "", + /* GPIO0_C */ + "PIN_11", /* GPIO0_C0 */ + "PIN_13", /* GPIO0_C1 */ + "", "", "", "", "", "", + /* GPIO0_D */ + "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A */ + "", "", "", "", "", "", "", "", + /* GPIO1_B */ + "", "", "", "", "", "", "", "", + /* GPIO1_C */ + "", "", "", "", "", "", "", "", + /* GPIO1_D */ + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A */ + "", "", "", "", "", "", "", "", + /* GPIO2_B */ + "", "", "", "", "", "", "", "", + /* GPIO2_C */ + "", "", "", "", "", "", "", "", + /* GPIO2_D */ + "PIN_21", /* GPIO2_D0 */ + "PIN_19", /* GPIO2_D1 */ + "PIN_24", /* GPIO2_D2 */ + "PIN_23", /* GPIO2_D3 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A */ + "", "", "", "", "", "", "", "", + /* GPIO3_B */ + "", "", + "PIN_15", /* GPIO3_B2 */ + "", "", + "PIN_5", /* GPIO3_B5 */ + "PIN_3", /* GPIO3_B6 */ + "", + /* GPIO3_C */ + "", "", "", "", "", "", + "PIN_16", /* GPIO3_C6 */ + "PIN_18", /* GPIO3_C7 */ + /* GPIO3_D */ + "PIN_12", /* GPIO3_D0 */ + "PIN_22", /* GPIO3_D1 */ + "PIN_26", /* GPIO3_D2 */ + "PIN_32", /* GPIO3_D3 */ + "PIN_36", /* GPIO3_D4 */ + "PIN_35", /* GPIO3_D5 */ + "PIN_8", /* GPIO3_D6 */ + "PIN_10"; /* GPIO3_D7 */ +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A */ + "", "", "", "", "", "", "", "", + /* GPIO4_B */ + "", "", "", "", "", "", + "PIN_31", /* GPIO4_B6 */ + "", + /* GPIO4_C */ + "", + "PIN_29", /* GPIO4_C1 */ + "", "", "", + "", "", "", + /* GPIO4_D */ + "", "", "", "", "", "", "", ""; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sfc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi new file mode 100644 index 000000000000..f355cd859791 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + /delete-node/ adc-keys; + /delete-node/ nandc@fe330000; + /delete-node/ sdio-pwrseq; + /delete-node/ vcc3v3-lcd0-n; + /delete-node/ vcc3v3-lcd1-n; + /delete-node/ wireless-bluetooth; + /delete-node/ wireless-wlan; + + leds: leds { + power_led: power { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; + + /delete-node/ gt1x@14; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c5 { + status = "disabled"; + + /delete-node/ mxc6655xa@15; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + /delete-node/ mxc6655xa; + /delete-node/ touch; + /delete-node/ wifi-enable-h; + /delete-node/ wireless-bluetooth; + + fspi { + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio4-supply = <&vcc_1v8>; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&rng { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +};