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hdmitx: update the phy setting for TM2 [2/2]

Browse Source 
PD#SWPL-10703

Problem:
HDMITX Eye Diagram of TM2 test fail

Solution:
Optimize the phy setting;

Verify:
TM2

Change-Id: Ib9f948aa85fe189754d7da002727309e7e32ca18
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
This commit is contained in:
yicheng shen
2019-07-15 02:53:07 -04:00
committed by Tao Zeng
parent b1add6112d
commit 3705fb2576
2 changed files with 4 additions and 9 deletions
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11
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1902,23 +1902,18 @@ static void set_phy_by_mode(unsigned int mode)
case MESON_CPU_ID_TM2:
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
if (hdev->dongle_mode)
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33EB65c4);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case 2: /* 2.97Gbps */
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb6262);
if (hdev->dongle_mode)
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0,
0x33eb4262);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb42a5);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case 3: /* 1.485Gbps, and below */
default:
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;

2
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -27,7 +27,7 @@
#include <linux/pinctrl/consumer.h>
/* HDMITX driver version */
#define HDMITX_VER "20190624"
#define HDMITX_VER "20190715"
/* chip type */
#define MESON_CPU_ID_M8B 0