From 37158d1f2b8335575e8e7adea28ebf2aa021bdd5 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 21 Oct 2019 16:13:03 +0800 Subject: [PATCH] clk: rockchip: rk3128: Change SCLK_DDRC to composite Change-Id: I6aeae7103c1eaed0b4515d8d11863c4b190b6918 Signed-off-by: Liang Chen Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3128.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 2bcbfe0a9795..34b3695ef582 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -212,9 +212,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(0), 2, GFLAGS), GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 2, GFLAGS), - COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), - FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2), + COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0, + RK2928_CLKSEL_CON(26), 8, 2, 0, 2, + ROCKCHIP_DDRCLK_SIP_V2), FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2), /* PD_CORE */