diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi
index 6cb6214910e2..f8ad509e7596 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi
@@ -40,8 +40,10 @@
 
 	sound1 {
 		compatible = "simple-audio-card";
+		simple-audio-card,format = "dsp_a";
+		simple-audio-card,bitclock-inversion;
+		simple-audio-card,mclk-fs = <256>;
 		simple-audio-card,name = "rockchip,bt";
-		simple-audio-card,format = "i2s";
 		simple-audio-card,cpu {
 			sound-dai = <&i2s2_2ch>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 01638faaaaad..43d450d2f2ca 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -209,6 +209,7 @@
 		pvtpll_isp: pvtpll-isp@21c60000 {
 			compatible = "rockchip,rv1126b-isp-pvtpll";
 			reg = <0x21c60000 0x100>;
+			rockchip,cru = <&cru>;
 			#clock-cells = <0>;
 			clock-output-names = "clk_isp_pvtpll";
 			assigned-clocks = <&pvtpll_isp>;
@@ -227,6 +228,7 @@
 		pvtpll_aisp: pvtpll-aisp@21fc0000 {
 			compatible = "rockchip,rv1126b-aisp-pvtpll";
 			reg = <0x21fc0000 0x100>;
+			rockchip,cru = <&cru>;
 			#clock-cells = <0>;
 			clock-output-names = "clk_vcp_pvtpll";
 			assigned-clocks = <&pvtpll_aisp>;
@@ -496,6 +498,10 @@
 	dmc_opp_table: dmc-opp-table {
 		compatible = "operating-points-v2";
 
+		rockchip,temp-hysteresis = <5000>;
+		rockchip,low-temp = <10000>;
+		rockchip,low-temp-min-volt = <950000>;
+
 		opp-1560000000 {
 			opp-hz = /bits/ 64 <1560000000>;
 			opp-microvolt = <900000 900000 950000>;
diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c
index 23b41c88c279..b264274d912c 100644
--- a/drivers/clk/rockchip/clk-pvtpll.c
+++ b/drivers/clk/rockchip/clk-pvtpll.c
@@ -33,10 +33,10 @@
 #define RV1103B_PVTPLL_MAX_LENGTH		0x1ff
 #define RV1103B_PVTPLL_GCK_CNT_AVG		0x54
 
-#define RV1126B_NPUCRU_NPU_CLKSEL_CON0		0x90300
-#define RV1126B_CLK_NPU_PVTPLL			BIT(0)
-#define RV1126B_CLK_NPU_PVTPLL_SRC_SEL_OFFSET	0
-#define RV1126B_CLK_NPU_PVTPLL_SRC_SEL_MASK	0x1
+#define RV1126B_PVTPLL_NORMAL_MODE		0x1
+#define RV1126B_PVTPLL_SLOW_MODE		0
+#define RV1126B_PVTPLL_MODE_SHIFT		0
+#define RV1126B_PVTPLL_MODE_MASK		0x1
 
 #define RK3506_GRF_CORE_PVTPLL_CON0_L		0x00
 #define RK3506_GRF_CORE_PVTPLL_CON0_H		0x04
@@ -59,6 +59,7 @@ struct pvtpll_table {
 };
 
 struct rockchip_clock_pvtpll_info {
+	const struct clk_ops *clk_ops;
 	unsigned int table_size;
 	struct pvtpll_table *table;
 	unsigned int jm_table_size;
@@ -66,6 +67,8 @@ struct rockchip_clock_pvtpll_info {
 	unsigned int pvtpll_adjust_factor;
 	unsigned int calibrate_length_step;
 	unsigned int calibrate_freq_per_step;
+	unsigned int mode_offset;
+	bool is_always_on;
 	int (*config)(struct rockchip_clock_pvtpll *pvtpll,
 		      struct pvtpll_table *table);
 	int (*pvtpll_calibrate)(struct rockchip_clock_pvtpll *pvtpll);
@@ -249,26 +252,22 @@ static int rv1103b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll,
 	return ret;
 }
 
-static int rv1126b_npu_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll,
+static int rv1126b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll,
 				  struct pvtpll_table *table)
 {
 	u32 val;
 	int ret = 0;
 
-	ret = regmap_read(pvtpll->regmap_cru, RV1126B_NPUCRU_NPU_CLKSEL_CON0, &val);
+	ret = rv1103b_pvtpll_configs(pvtpll, table);
 	if (ret)
 		return ret;
 
-	if (table->rate == pvtpll->cur_rate && (val & RV1126B_CLK_NPU_PVTPLL))
+	if (!pvtpll->regmap_cru)
 		return 0;
 
-	val = HIWORD_UPDATE(RV1126B_CLK_NPU_PVTPLL, RV1126B_CLK_NPU_PVTPLL_SRC_SEL_MASK,
-			    RV1126B_CLK_NPU_PVTPLL_SRC_SEL_OFFSET);
-	ret = regmap_write(pvtpll->regmap_cru, RV1126B_NPUCRU_NPU_CLKSEL_CON0, val);
-	if (ret)
-		return ret;
-
-	return rv1103b_pvtpll_configs(pvtpll, table);
+	val = HIWORD_UPDATE(RV1126B_PVTPLL_NORMAL_MODE, RV1126B_PVTPLL_MODE_MASK,
+			    RV1126B_PVTPLL_MODE_SHIFT);
+	return regmap_write(pvtpll->regmap_cru, pvtpll->info->mode_offset, val);
 }
 
 static int rk3506_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll,
@@ -362,31 +361,75 @@ static long rockchip_clock_pvtpll_round_rate(struct clk_hw *hw, unsigned long ra
 	return rate;
 }
 
-static int clk_gate_enable(struct clk_hw *hw)
+static int rv1126b_pvtpll_enable(struct clk_hw *hw)
 {
 	struct rockchip_clock_pvtpll *pvtpll;
 	struct pvtpll_table *table;
-	int ret = 0;
+	u32 val = 0;
 
 	pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw);
-
-	if (!pvtpll || !pvtpll->regmap_cru)
-		return 0;
-
 	table = rockchip_get_pvtpll_settings(pvtpll, pvtpll->cur_rate);
 	if (!table)
 		return 0;
 
-	ret = pvtpll->info->config(pvtpll, table);
+	regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, &val);
+	if (!(val & RV1103B_GCK_EN))
+		return pvtpll->info->config(pvtpll, table);
 
-	return ret;
+	return 0;
+}
+
+static void rv1126b_pvtpll_disable(struct clk_hw *hw)
+{
+	struct rockchip_clock_pvtpll *pvtpll;
+	u32 val;
+	int ret;
+
+	pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw);
+	if (!pvtpll->regmap_cru)
+		return;
+
+	val = HIWORD_UPDATE(RV1126B_PVTPLL_SLOW_MODE, RV1126B_PVTPLL_MODE_MASK,
+			    RV1126B_PVTPLL_MODE_SHIFT);
+	ret = regmap_write(pvtpll->regmap_cru,  pvtpll->info->mode_offset, val);
+	if (ret)
+		return;
+	regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, RV1103B_GCK_EN << 16);
+}
+
+static int rv1126b_pvtpll_is_enabled(struct clk_hw *hw)
+{
+	struct rockchip_clock_pvtpll *pvtpll;
+	u32 val = 0;
+
+	pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw);
+	regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, &val);
+
+	return (val & RV1103B_GCK_EN);
 }
 
 static const struct clk_ops clock_pvtpll_ops = {
 	.recalc_rate = rockchip_clock_pvtpll_recalc_rate,
 	.round_rate = rockchip_clock_pvtpll_round_rate,
 	.set_rate = rockchip_clock_pvtpll_set_rate,
-	.enable = clk_gate_enable,
+};
+
+static const struct clk_ops rv1126b_pvtpll_ops = {
+	.recalc_rate = rockchip_clock_pvtpll_recalc_rate,
+	.round_rate = rockchip_clock_pvtpll_round_rate,
+	.set_rate = rockchip_clock_pvtpll_set_rate,
+	.enable = rv1126b_pvtpll_enable,
+	.disable = rv1126b_pvtpll_disable,
+	.is_enabled = rv1126b_pvtpll_is_enabled,
+};
+
+/* Remove is_enabled for fixing clk_summary issue */
+static const struct clk_ops rv1126b_npu_pvtpll_ops = {
+	.recalc_rate = rockchip_clock_pvtpll_recalc_rate,
+	.round_rate = rockchip_clock_pvtpll_round_rate,
+	.set_rate = rockchip_clock_pvtpll_set_rate,
+	.enable = rv1126b_pvtpll_enable,
+	.disable = rv1126b_pvtpll_disable,
 };
 
 static int clock_pvtpll_regitstor(struct device *dev,
@@ -398,7 +441,10 @@ static int clock_pvtpll_regitstor(struct device *dev,
 	init.num_parents = 0;
 	init.flags = CLK_GET_RATE_NOCACHE;
 	init.name = "pvtpll";
-	init.ops = &clock_pvtpll_ops;
+	if (pvtpll->info->clk_ops)
+		init.ops = pvtpll->info->clk_ops;
+	else
+		init.ops = &clock_pvtpll_ops;
 
 	pvtpll->hw.init = &init;
 
@@ -658,46 +704,56 @@ static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = {
 };
 
 static const struct rockchip_clock_pvtpll_info rv1126b_aisp_pvtpll_data = {
-	.config = rv1103b_pvtpll_configs,
+	.clk_ops = &rv1126b_pvtpll_ops,
+	.config = rv1126b_pvtpll_configs,
 	.table_size = ARRAY_SIZE(rv1126b_aisp_pvtpll_table),
 	.table = rv1126b_aisp_pvtpll_table,
 	.calibrate_length_step = 4,
 	.calibrate_freq_per_step = 20,
 	.pvtpll_calibrate = rv1103b_pvtpll_calibrate,
+	.mode_offset = 0xb0300,
 };
 
 static const struct rockchip_clock_pvtpll_info rv1126b_core_pvtpll_data = {
-	.config = rv1103b_pvtpll_configs,
+	.config = rv1126b_pvtpll_configs,
 	.table_size = ARRAY_SIZE(rv1126b_core_pvtpll_table),
 	.table = rv1126b_core_pvtpll_table,
 	.pvtpll_adjust_factor = 4,
 	.pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear,
+	.mode_offset = 0x30300,
+	.is_always_on = true,
 };
 
 static const struct rockchip_clock_pvtpll_info rv1126b_enc_pvtpll_data = {
-	.config = rv1103b_pvtpll_configs,
+	.config = rv1126b_pvtpll_configs,
 	.table_size = ARRAY_SIZE(rv1126b_enc_pvtpll_table),
 	.table = rv1126b_enc_pvtpll_table,
 	.calibrate_length_step = 8,
 	.calibrate_freq_per_step = 20,
 	.pvtpll_calibrate = rv1103b_pvtpll_calibrate,
+	.mode_offset = 0x80300,
+	.is_always_on = true,
 };
 
 static const struct rockchip_clock_pvtpll_info rv1126b_isp_pvtpll_data = {
-	.config = rv1103b_pvtpll_configs,
+	.clk_ops = &rv1126b_pvtpll_ops,
+	.config = rv1126b_pvtpll_configs,
 	.table_size = ARRAY_SIZE(rv1126b_isp_pvtpll_table),
 	.table = rv1126b_isp_pvtpll_table,
 	.calibrate_length_step = 8,
 	.calibrate_freq_per_step = 20,
 	.pvtpll_calibrate = rv1103b_pvtpll_calibrate,
+	.mode_offset = 0x70300,
 };
 
 static const struct rockchip_clock_pvtpll_info rv1126b_npu_pvtpll_data = {
-	.config = rv1126b_npu_pvtpll_configs,
+	.clk_ops = &rv1126b_npu_pvtpll_ops,
+	.config = rv1126b_pvtpll_configs,
 	.table_size = ARRAY_SIZE(rv1126b_npu_pvtpll_table),
 	.table = rv1126b_npu_pvtpll_table,
 	.pvtpll_adjust_factor = 6,
 	.pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear,
+	.mode_offset = 0x90300,
 };
 
 static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = {
@@ -826,13 +882,14 @@ static int rockchip_clock_pvtpll_resume(struct device *dev)
 	struct rockchip_clock_pvtpll *pvtpll = dev_get_drvdata(dev);
 	struct pvtpll_table *table;
 
+	if (!pvtpll->info->is_always_on)
+		return 0;
+
 	table = rockchip_get_pvtpll_settings(pvtpll, pvtpll->cur_rate);
 	if (!table)
 		return 0;
 
-	pvtpll->info->config(pvtpll, table);
-
-	return 0;
+	return pvtpll->info->config(pvtpll, table);
 }
 
 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_clock_pvtpll_pm_ops, NULL,
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 95f6b8611dc9..96241e619f91 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -2755,8 +2755,15 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 		}
 	}
 
-	if (hdmi->panel)
+	if (hdmi->panel) {
+		hdmi->support_hdmi = true;
+		hdmi->sink_is_hdmi = true;
+		hdmi->sink_has_audio = true;
+		info->hdmi.scdc.supported = true;
+		info->hdmi.scdc.scrambling.supported = true;
+		info->max_tmds_clock = HDMI20_MAX_TMDSCLK_KHZ;
 		return drm_panel_get_modes(hdmi->panel, connector);
+	}
 
 	if (hdmi->next_bridge && hdmi->next_bridge->ops & DRM_BRIDGE_OP_MODES)
 		return drm_bridge_get_modes(hdmi->next_bridge, connector);
@@ -2826,6 +2833,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 		kfree(drm_edid);
 	} else {
 		hdmi->support_hdmi = true;
+		hdmi->sink_is_hdmi = true;
 		hdmi->sink_has_audio = true;
 
 		if (hdmi->plat_data->split_mode) {
@@ -2855,6 +2863,9 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 		info->edid_hdmi_ycbcr444_dc_modes = 0;
 		info->hdmi.y420_dc_modes = 0;
 		info->color_formats = 0;
+		info->hdmi.scdc.supported = true;
+		info->hdmi.scdc.scrambling.supported = true;
+		info->max_tmds_clock = HDMI20_MAX_TMDSCLK_KHZ;
 
 		dev_info(hdmi->dev, "failed to get edid\n");
 	}
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f8ecb01f355b..9bf44962097c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -592,6 +592,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 		dw_mipi_dsi_video_mode_config(dsi);
 	} else {
+		u32 val = 0;
+
+		/* DSI work in command mode, using long packet DCS commands
+		 * WMC and WMS to send video signals at high speed.
+		 */
+		val = dsi_read(dsi, DSI_CMD_MODE_CFG);
+		val &= ~DCS_LW_TX_LP;
+		dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+
 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 	}
 
diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index 77fc7c58e413..e28a0a0de2ae 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -343,9 +343,7 @@ struct rockchip_thermal_data {
 #define RV1126B_UNLOCK_VALUE_MASK		(0xff << 16)
 #define RV1126B_UNLOCK_TRIGGER			BIT(8)
 #define RV1126B_UNLOCK_TRIGGER_MASK		(BIT(8) << 16)
-#define RV1126B_DEF_WIDTH			0x00010001
-#define RV1126B_TARGET_WIDTH			24000
-#define RV1126B_DEF_BIAS			32
+#define RV1126B_MAX_BIAS			0x7f
 #define RV1126B_BIAS_MASK			(0x7f << 16)
 #define RV1126B_SW_CTRL				0x8028
 #define RV1126B_SW_CTRL_MASK			(0x8078 << 16)
@@ -1690,19 +1688,16 @@ static void rv1126b_tsadc_phy_init(struct device *dev, struct regmap *grf,
 				   void __iomem *reg, struct phy_config *phy_cfg)
 {
 	u32 val = 0;
-	u32 width = 0;
 
 	if (!phy_cfg->bias) {
-		phy_cfg->bias = RV1126B_DEF_BIAS;
-		regmap_read(grf, RV1126B_GRF_TSADC_ST1, &val);
-		if (val && val != RV1126B_DEF_WIDTH) {
-			width = (val & 0x0000ffff) + ((val & 0xffff0000) >> 16);
-			phy_cfg->bias = width * RV1126B_DEF_BIAS / RV1126B_TARGET_WIDTH;
-		}
-		dev_info(dev, "width=0x%x, bias=0x%x\n", val, phy_cfg->bias);
+		regmap_read(grf, RV1126B_GRF_TSADC_CON6, &val);
+		phy_cfg->bias = val & RV1126B_MAX_BIAS;
+	} else {
+		regmap_write(grf, RV1126B_GRF_TSADC_CON6,
+			     phy_cfg->bias | RV1126B_BIAS_MASK);
 	}
-	regmap_write(grf, RV1126B_GRF_TSADC_CON6,
-		     phy_cfg->bias | RV1126B_BIAS_MASK);
+	regmap_read(grf, RV1126B_GRF_TSADC_ST1, &val);
+	dev_info(dev, "width=0x%x, bias=0x%x\n", val, phy_cfg->bias);
 	regmap_write(grf, RV1126B_GRF_TSADC_CON6,
 		     RV1126B_CH_EN | RV1126B_CH_EN_MASK);
 	regmap_write(grf, RV1126B_GRF_TSADC_CON0,
@@ -1836,7 +1831,6 @@ static const struct rockchip_tsadc_chip rv1126_tsadc_data = {
 static const struct rockchip_tsadc_chip rv1126b_tsadc_data = {
 	.chn_id = {0, 1}, /* cpu, npu */
 	.chn_num = 2, /* two channels for tsadc */
-	.conversion_time = 2000, /* us */
 	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
 	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
 	.tshut_temp = 95000,