diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c80035f10ddd..39ed7ff6dca8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -847,6 +847,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1109-38-v10-spi-nand.dtb \
 	rv1109-ai-cam-ddr3-v1.dtb \
 	rv1109-evb-ddr3-v12-facial-gate.dtb \
+	rv1109-evb-ddr3-v13-facial-gate.dtb \
 	rv1109-fpga.dtb \
 	rv1126-38x38-v10-emmc.dtb \
 	rv1126-38x38-v10-spi-nor.dtb \
diff --git a/arch/arm/boot/dts/rv1109-evb-ddr3-v13-facial-gate.dts b/arch/arm/boot/dts/rv1109-evb-ddr3-v13-facial-gate.dts
new file mode 100644
index 000000000000..e1870d44e683
--- /dev/null
+++ b/arch/arm/boot/dts/rv1109-evb-ddr3-v13-facial-gate.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+/dts-v1/;
+#include "rv1109-evb-ddr3-v12-facial-gate.dts"
+
+/ {
+	model = "Rockchip RV1109 EVB DDR3 V13 Facial Gate Board";
+	compatible = "rockchip,rv1109-evb-ddr3-v13-facial-gate", "rockchip,rv1126";
+};
+
+&backlight {
+	pwms = <&pwm0 0 25000 0>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "disabled";
+};
+
+&u2phy0 {
+	vup-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
+};