From 37e328a6d49b99e7ea4612173228da61e37e3668 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sun, 3 Mar 2024 13:57:05 +0800 Subject: [PATCH] dt-bindings: spi: rockchip-sfc: Add sfc-cs-gpios property Part of ROCKCHIP SOC FSPI ip has only one CSN function io, and since the limitation of spi-mem which is not support cs-gpios, add sfc-cs-gpios for cs extension. Change-Id: Ie3614e306a3c6eb5dff0631b13a58243abfc7d23 Signed-off-by: Jon Lin --- Documentation/devicetree/bindings/spi/rockchip-sfc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml index 339fb39529f3..39f73a3ad626 100644 --- a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml @@ -59,6 +59,11 @@ required: - clocks - clock-names +Optional properties: + - sfc-cs-gpios: specifies the gpio pins to be used for chipselects. + The gpios will be referred to as reg = in the SPI child nodes. + If unspecified, a single SPI device without a chip select can be used. + unevaluatedProperties: false examples: @@ -76,6 +81,7 @@ examples: pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; pinctrl-names = "default"; power-domains = <&power PX30_PD_MMC_NAND>; + sfc-cs-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>, <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>;