diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index 71a043f75a9a..a5ff16b76958 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
 static dev_t di_devno;
 static struct class *di_clsp;
 
-static const char version_s[] = "2019-02-26a sm1 buring up test";
+static const char version_s[] = "2019-03-18a";
 
 static int bypass_state = 1;
 static int bypass_all;
@@ -2100,7 +2100,8 @@ static int di_init_buf(int width, int height, unsigned char prog_flag)
 		mtn_size = (mtn_width * canvas_height)*4/16;
 		count_size = (mtn_width * canvas_height)*4/16;
 		mv_size = (mv_width * canvas_height)/5;
-		mc_size = canvas_height;
+		mc_size = roundup(canvas_height >> 1, canvas_align_width) << 1;
+
 		if (mc_mem_alloc) {
 			di_buf_size = nr_size + mtn_size + count_size +
 				mv_size + mc_size;
@@ -2153,6 +2154,7 @@ static int di_init_buf(int width, int height, unsigned char prog_flag)
 			di_buf->canvas_width[NR_CANVAS] = nr_canvas_width;
 			di_buf->canvas_width[MTN_CANVAS] = mtn_canvas_width;
 			di_buf->canvas_width[MV_CANVAS] = mv_canvas_width;
+
 			if (prog_flag) {
 				di_buf->canvas_height = canvas_height;
 				di_buf->nr_adr = de_devp->mem_start +
@@ -2160,6 +2162,9 @@ static int di_init_buf(int width, int height, unsigned char prog_flag)
 				di_buf->canvas_config_flag = 1;
 			} else {
 				di_buf->canvas_height = (canvas_height>>1);
+				di_buf->canvas_height =
+					roundup(di_buf->canvas_height,
+					canvas_align_width);
 				di_buf->nr_adr = de_devp->mem_start +
 					di_buf_size * i;
 				di_buf->mtn_adr = de_devp->mem_start +
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index fc9c0dac6a4c..c27780b7cc50 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -330,6 +330,11 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr,
 	if (!lmv_lock_win_en)
 		return;
 
+    if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
+		pr_debug("%s: only support G12A and after chips.\n", __func__);
+		return;
+	}
+
 	tmp = di_vmap(mcinfo_adr, mcinfo_size, &bflg_vmap);
 	if (tmp == NULL) {
 		di_print("err:di_vmap failed\n");
@@ -340,11 +345,12 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr,
 	for (i = 0; i < (vf_height>>1); i++) {
 		lmvs_init(&lines_mv[i], *(mcinfo_vadr+i));
 		j = i + (vf_height>>1);
-		lmvs_init(&lines_mv[j], *(mcinfo_vadr+i+272));
+		/*288 = (canvas height(1088)/2 align to 64)*/
+		lmvs_init(&lines_mv[j], *(mcinfo_vadr+i+288));
 		if (pr_mcinfo_cnt && j < (vf_height - 10) &&
 			j > (vf_height - offset_lmv)) {
 			pr_info("MCINFO[%u]=0x%x\t", j,
-				*(mcinfo_vadr + i + 272));
+				*(mcinfo_vadr + i + 288));
 			if (i%16 == 0)
 				pr_info("\n");
 		}
@@ -488,6 +494,10 @@ void di_hw_init(bool pd_enable, bool mc_enable)
 		fifo_size_di = 0x120;
 	}
 
+	/*enable lock win, suggestion from vlsi zheng.bao*/
+	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+		lmv_lock_win_en = 1;
+
 	DI_Wr(VD1_IF0_LUMA_FIFO_SIZE, fifo_size_vpp);
 	DI_Wr(VD2_IF0_LUMA_FIFO_SIZE, fifo_size_vpp);
 	/* 1a83 is vd2_if0_luma_fifo_size */
@@ -1275,7 +1285,7 @@ void enable_mc_di_pre_g12(struct DI_MC_MIF_s *mcinford_mif,
 
 	RDMA_WR_BITS(MCINFRD_SCOPE_X, mcinford_mif->size_x, 16, 13);
 	RDMA_WR_BITS(MCINFRD_SCOPE_Y, mcinford_mif->size_y, 16, 13);
-	RDMA_WR_BITS(MCINFRD_CTRL1, mcvecwr_mif->canvas_num, 16, 8);
+	RDMA_WR_BITS(MCINFRD_CTRL1, mcinford_mif->canvas_num, 16, 8);
 	RDMA_WR_BITS(MCINFRD_CTRL1, 2, 0, 3);
 
 	RDMA_WR_BITS(MCVECWR_X, mcvecwr_mif->size_x, 0, 13);