From 38949a9e60ebd8f2bf02a1fcddf73d0140ba0299 Mon Sep 17 00:00:00 2001 From: "charles.park" Date: Tue, 17 Jan 2017 14:38:59 +0900 Subject: [PATCH] ODROID-XU4: SPI1 clock setup Change-Id: I0d9ec6040409685d2d94baa9172b043c9625f079 --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 5 +++++ drivers/clk/samsung/clk-exynos5420.c | 6 +++--- include/dt-bindings/clock/exynos5420.h | 4 ++++ 3 files changed, 12 insertions(+), 3 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.c mode change 100644 => 100755 include/dt-bindings/clock/exynos5420.h diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 0437caefc122..05c7256a78f6 100755 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -55,6 +55,11 @@ &spi_1 { status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_SPI1>, <&clock CLK_DOUT_SPI1>; + assigned-clock-parents = <&clock CLK_MOUT_DPLL>; + assigned-clock-rates = <0>, <80000000>; + samsung,spi-src-clk = <0>; num-cs = <2>; cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>; diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c old mode 100644 new mode 100755 index 71b201d97f2e..202d40a987fb --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -704,7 +704,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), - MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), + MUX(CLK_MOUT_DPLL, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, @@ -788,7 +788,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), - MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), + MUX(CLK_MOUT_SPI1, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), /* ISP Block */ @@ -899,7 +899,7 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { /* SPI */ DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), - DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), + DIV(CLK_DOUT_SPI1, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), /* Mfc Block */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h old mode 100644 new mode 100755 index 6fd21c291416..2706e8c5a382 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -218,6 +218,10 @@ #define CLK_MOUT_BPLL 655 #define CLK_MOUT_MX_MSPLL_CCORE 656 +#define CLK_MOUT_DPLL 700 +#define CLK_MOUT_SPI1 701 +#define CLK_DOUT_SPI1 702 + /* divider clocks */ #define CLK_DOUT_PIXEL 768 #define CLK_DOUT_ACLK400_WCORE 769