From 38f95dea7201e110e9ba352f890b0482f89caea2 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 17 Dec 2021 11:42:05 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add volt-mem-read-margin for gpu Signed-off-by: Finley Xiao Change-Id: Ib6b50a308321e5940a938d55099673297ec30fb7 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index ed5282e9e073..bd4238428def 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1000,6 +1000,16 @@ gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; + clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_GRF>; + clock-names = "clk", "pclk"; + rockchip,grf = <&gpu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 585000 4 + >; + opp-198000000 { opp-hz = /bits/ 64 <198000000>; opp-microvolt = <750000 750000 950000>, @@ -1224,6 +1234,11 @@ reg = <0x0 0xfd592000 0x0 0x100>; }; + gpu_grf: syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf", "syscon"; + reg = <0x0 0xfd5a0000 0x0 0x100>; + }; + vop_grf: syscon@fd5a4000 { compatible = "rockchip,rk3588-vop-grf", "syscon"; reg = <0x0 0xfd5a4000 0x0 0x2000>;