From 395d9a60183c0601bc4bd613905f75780b35fd2f Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Fri, 3 Dec 2021 15:47:39 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Fix sata clock The sata need pipe clock for the interface and asic clock for the phy. Signed-off-by: Yifeng Zhao Change-Id: I6069bd653a3f22da8ade0cab002c5346c9880cef --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 10 ++++++---- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 20 ++++++++++++-------- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 0d618d694842..2aaeec40b6b5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -673,8 +673,9 @@ compatible = "snps,dwc-ahci"; reg = <0 0xfe220000 0 0x1000>; clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>; - clock-names = "sata", "pmalive", "rxoob", "ref"; + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; interrupts = ; interrupt-names = "hostc"; phys = <&combphy1_ps PHY_TYPE_SATA>; @@ -763,8 +764,9 @@ compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; #phy-cells = <1>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>; - clock-names = "refclk", "apbclk"; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; assigned-clock-rates = <100000000>; resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 35aac3e419d4..35be4eec5bcf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -3333,8 +3333,9 @@ compatible = "snps,dwc-ahci"; reg = <0 0xfe210000 0 0x1000>; clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; - clock-names = "sata", "pmalive", "rxoob", "ref"; + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; interrupts = ; interrupt-names = "hostc"; phys = <&combphy0_ps PHY_TYPE_SATA>; @@ -3348,8 +3349,9 @@ compatible = "snps,dwc-ahci"; reg = <0 0xfe230000 0 0x1000>; clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; - clock-names = "sata", "pmalive", "rxoob", "ref"; + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; interrupts = ; interrupt-names = "hostc"; phys = <&combphy2_psu PHY_TYPE_SATA>; @@ -4446,8 +4448,9 @@ compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; #phy-cells = <1>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; - clock-names = "refclk", "apbclk"; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; assigned-clock-rates = <100000000>; resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; @@ -4461,8 +4464,9 @@ compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee20000 0x0 0x100>; #phy-cells = <1>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; - clock-names = "refclk", "apbclk"; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; assigned-clock-rates = <100000000>; resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;