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dv: dolby tv core need bitmatch [1/1]

Browse Source 
PD#SWPL-6655

Problem:
tm2 tvcore not bitmatch

Solution:
1.Config VIU_VD1_FMT_CTRL for tm2
2.Config DIAG_CTRL, CRC_CTRL and CM_CRC reg for tm2
3.Config DOLBY_PATH_CTRL for tm2

Verify:
Verified on tm2

Change-Id: I56a086c498ed4d3bf2f43a4639c79546072d586b
Signed-off-by: yao liu <yao.liu@amlogic.com>
This commit is contained in:
yao liu
2019-09-05 07:12:38 -04:00
committed by Jianxin Pan
parent 190492f6a9
commit 3969e3a6fd
3 changed files with 97 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
View File

@@ -1715,9 +1715,12 @@ static int tv_dolby_core1_set(
else
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL5, 0, 4, 1);
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL6, 1, 20, 1);
/* bypass dither */
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL6, 1, 25, 1);
/*set diag reg to 0xb can bypass dither, not need set swap ctrl6 */
if (!is_meson_tm2_tvmode()) {
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL6, 1, 20, 1);
/* bypass dither */
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL6, 1, 25, 1);
}
if (src_chroma_format == 2)
VSYNC_WR_DV_REG_BITS(DOLBY_TV_SWAP_CTRL6, 1, 29, 1);
else if (src_chroma_format == 1)
@@ -1736,18 +1739,44 @@ static int tv_dolby_core1_set(
/* vd2 to vpp */
1, 17, 1);
if (dolby_vision_core1_on
&& !bypass_core1)
if (dolby_vision_core1_on &&
!bypass_core1) {
if (is_meson_tm2_tvmode()) {
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 8, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 10, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
0, 16, 1);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
0, 20, 1);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 24, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
0, 0, 2);
} else
VSYNC_WR_DV_REG_BITS(
VIU_MISC_CTRL1,
/* enable core 1 */
0, 16, 1);
else if (dolby_vision_core1_on
&& bypass_core1)
VSYNC_WR_DV_REG_BITS(
VIU_MISC_CTRL1,
/* bypass core 1 */
1, 16, 1);
} else if (dolby_vision_core1_on &&
bypass_core1) {
if (is_meson_tm2_tvmode()) {
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
3, 0, 2);
} else
VSYNC_WR_DV_REG_BITS(
VIU_MISC_CTRL1,
/* bypass core 1 */
1, 16, 1);
}
if (dolby_vision_run_mode != 0xff)
run_mode = dolby_vision_run_mode;
@@ -3177,7 +3206,8 @@ void enable_dolby_vision(int enable)
/* 10->12 after gainoff */
VSYNC_WR_DV_REG(
VPP_DAT_CONV_PARA1, 0x20002000);
WRITE_VPP_DV_REG(0x33e7, 0xb);
WRITE_VPP_DV_REG(DOLBY_TV_DIAG_CTRL,
0xb);
} else {
/* bypass all video effect */
if (dolby_vision_flags
@@ -3537,7 +3567,27 @@ void enable_dolby_vision(int enable)
DOLBY_PATH_CTRL,
/* enable core1 */
0, 0, 1);
else
else if (is_meson_tm2_tvmode()) {
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 8, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 10, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
0, 16, 1);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
0, 20, 1);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
1, 24, 2);
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
/* enable core1 */
0, 0, 2);
} else
VSYNC_WR_DV_REG_BITS(
VIU_MISC_CTRL1,
0,
@@ -3552,6 +3602,11 @@ void enable_dolby_vision(int enable)
DOLBY_PATH_CTRL,
/* disable core1 */
1, 0, 1);
else if (is_meson_tm2_tvmode())
VSYNC_WR_DV_REG_BITS(
DOLBY_PATH_CTRL,
/* disable core1 */
3, 0, 2);
else
VSYNC_WR_DV_REG_BITS(
VIU_MISC_CTRL1,
@@ -7672,8 +7727,8 @@ void tv_dolby_vision_insert_crc(bool print)
}
if (is_meson_tvmode()
&& !force_stb_mode) {
crc_enable = (READ_VPP_DV_REG(0x33e7) == 0xb);
crc = READ_VPP_DV_REG(0x33ef);
crc_enable = (READ_VPP_DV_REG(DOLBY_TV_DIAG_CTRL) == 0xb);
crc = READ_VPP_DV_REG(DOLBY_TV_OUTPUT_DM_CRC);
} else {
crc_enable = true; /* (READ_VPP_DV_REG(0x36fb) & 1); */
crc = READ_VPP_DV_REG(0x36fd);

3
drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h
View File

@@ -103,6 +103,9 @@
#define DOLBY_TV_AXI2DMA_CTRL3 (0xfd + CORETV_OFFSET)
#define DOLBY_TV_STATUS0 (0xfe + CORETV_OFFSET)
#define DOLBY_TV_STATUS1 (0xff + CORETV_OFFSET)
#define DOLBY_TV_DIAG_CTRL (0xe7 + CORETV_OFFSET)
#define DOLBY_TV_CRC_CTRL (0xea + CORETV_OFFSET)
#define DOLBY_TV_OUTPUT_DM_CRC (0xef + CORETV_OFFSET)
#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d

42
drivers/amlogic/media/video_sink/video.c
View File

@@ -4456,9 +4456,10 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
r = 0;
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
r = HFORMATTER_REPEAT |
HFORMATTER_YC_RATIO_2_1 |
HFORMATTER_EN |
@@ -4663,9 +4664,10 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
vformatter = VFORMATTER_EN;
else
vformatter = 0;
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -4770,9 +4772,10 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
<< VFORMATTER_PHASE_BIT) | VFORMATTER_EN |
hphase);
} else {
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -5032,9 +5035,10 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
(0x8 << VFORMATTER_PHASE_BIT) |
VFORMATTER_EN;
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
r |= HFORMATTER_REPEAT |
HFORMATTER_YC_RATIO_2_1 |
HFORMATTER_EN |
@@ -5197,9 +5201,10 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
vphase =
((type & VIDTYPE_VIU_422) ? 0x10 : 0x08) <<
VFORMATTER_PHASE_BIT;
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -5269,9 +5274,10 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
<< VFORMATTER_PHASE_BIT) |
VFORMATTER_EN | hphase);
} else {
if (is_meson_txlx_package_962X()
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
if ((is_meson_txlx_package_962X() ||
is_meson_tm2_cpu()) &&
!is_dolby_vision_stb_mode() &&
is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |