From 39dbfdc2ff82375c8d5c0eb52a462d713ffef69a Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 28 Apr 2025 10:12:42 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Add clk PCLK_PHP_ROOT to pcie30phy Configure pcie30phy phy_grf with clk PCLK_PHP_ROOT on. Change-Id: Ie3f9fa78aaf7b1098450ade48e6f0c9f09725869 Signed-off-by: Jon Lin --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index b4d5c06bdc1d..3ce608f103c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -773,8 +773,8 @@ compatible = "rockchip,rk3588-pcie3-phy"; reg = <0x0 0xfee80000 0x0 0x20000>; #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>, <&cru PCLK_PHP_ROOT>; + clock-names = "pclk", "phpclk"; resets = <&cru SRST_PCIE30_PHY>; reset-names = "phy"; rockchip,pipe-grf = <&php_grf>;