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clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling

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[ Upstream commit 63d56adf04 ]

GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously
made to reuse the same parent enum entry as GPLL0_OUT_MAIN
(.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2.

Resolve it by introducing its own entry in the parent enum and
correctly assigning it in disp_cc_parent_map_2[].

Fixes: cc517ea333 ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Konrad Dybcio
2023-04-14 13:06:36 +02:00
committed by Greg Kroah-Hartman
parent 203ab76704
commit 3c4f7d4990
1 changed files with 4 additions and 3 deletions
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7
drivers/clk/qcom/dispcc-qcm2290.c
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@@ -27,6 +27,7 @@ enum {
P_DISP_CC_PLL0_OUT_MAIN, P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK, P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_DIV,
P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN,
P_SLEEP_CLK, P_SLEEP_CLK,
}; };
@@ -83,7 +84,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
static const struct parent_map disp_cc_parent_map_2[] = { static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO_AO, 0 }, { P_BI_TCXO_AO, 0 },
{ P_GPLL0_OUT_MAIN, 4 }, { P_GPLL0_OUT_DIV, 4 },
}; };
static const struct clk_parent_data disp_cc_parent_data_2[] = { static const struct clk_parent_data disp_cc_parent_data_2[] = {
@@ -152,8 +153,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO_AO, 1, 0, 0), F(19200000, P_BI_TCXO_AO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
{ } { }
}; };