From 3c7205c50e98a1f35c3d8de52db384b339b62deb Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Wed, 13 Nov 2024 15:43:59 +0800
Subject: [PATCH] arm64: dts: rockchip: Add i2c nodes for rv1126b

It should be noted that the i2C2 does not have DMA capability.

Change-Id: I2c5cb9984613cae397908262a49c03034c395ac7
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 94 +++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 471d24bf292d..9f533676498b 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -26,6 +26,12 @@
 		gpio5 = &gpio5;
 		gpio6 = &gpio6;
 		gpio7 = &gpio7;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
 		serial0 = &uart0;
 	};
 
@@ -174,6 +180,19 @@
 		reg = <0x201a0000 0x50000>;
 	};
 
+	i2c2: i2c@20800000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x20800000 0x1000>;
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2m0_pins>;
+		status = "disabled";
+	};
+
 	uart0: serial@20810000 {
 		compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart";
 		reg = <0x20810000 0x100>;
@@ -264,6 +283,81 @@
 		clock-names = "pclk", "timer";
 	};
 
+	i2c0: i2c@21100000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x21100000 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+		clock-names = "i2c", "pclk";
+		dmas = <&dmac 29>, <&dmac 28>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0m0_pins>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@21110000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x21110000 0x1000>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+		clock-names = "i2c", "pclk";
+		dmas = <&dmac 31>, <&dmac 30>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1m0_pins>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@21120000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x21120000 0x1000>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+		clock-names = "i2c", "pclk";
+		dmas = <&dmac 35>, <&dmac 34>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3m0_pins>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@21130000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x21130000 0x1000>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+		clock-names = "i2c", "pclk";
+		dmas = <&dmac 37>, <&dmac 36>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c4m0_pins>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@21140000 {
+		compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c";
+		reg = <0x21140000 0x1000>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+		clock-names = "i2c", "pclk";
+		dmas = <&dmac 39>, <&dmac 38>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c5m0_pins>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@21201000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;