From 3c7417b499e34fe0d841a408bf9e0959b808d13f Mon Sep 17 00:00:00 2001
From: Luo Wei <lw@rock-chips.com>
Date: Mon, 26 Feb 2024 17:16:21 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588-vehicle-evb: maxim support 1080p
 display

dsi0->           ->max96752->720P
       max96789
dsi1->           ->max96752->1080P

dp0/edp0->          ->max96752->720P
           max96745
edp1/edp1->         ->max96752->720P

Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: I6f3c51ce40a6f11f0e135a6e649b2f5e7a8ba752
---
 ...ehicle-serdes-mfd-display-maxim-split.dtsi | 78 +++++++++----------
 1 file changed, 39 insertions(+), 39 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
index 7dd62e5150fe..44d71e44dd78 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
@@ -489,57 +489,57 @@
 			0322 0024
 			//Init Default
 			0326 00E4
-			//HSYNC_WIDTH_L
-			0385 0038
-			//VSYNC_WIDTH_L
-			0386 0008
+			//HSYNC_WIDTH_L	 HSYNC=32
+			0385 0020
+			//VSYNC_WIDTH_L	 VSYNC=2
+			0386 0002
 			//HSYNC_WIDTH_H/VSYNC_WIDTH_H
 			0387 0000
-			//VFP_L
+			//VFP_L	VFP=200
 			03A5 00C8
 			//VBP_H
 			03A7 0000
-			//VFP_H/VBP_L
-			03A6 0020
-			//VRES_L
+			//VFP_H/VBP_L VBP=8
+			03A6 0008
+			//VRES_L VRES=0X02D0=720
 			03A8 00D0
 			//VRES_H
 			03A9 0002
-			//HFP_L
+			//HFP_L	 HFP=56
 			03AA 0038
 			//HBP_H
-			03AC 0002
-			//HFP_H/HBP_L
-			03AB 0000
-			//HRES_L
+			03AC 0003
+			//HFP_H/HBP_L(4bit)	HBP=56
+			03AB 0008
+			//HRES_L HRES=0X0780=1920
 			03AD 0080
 			//HRES_H
 			03AE 0007
 			//Disable FIFO/DESKEW_EN
 			03A4 00C0
-			//HSYNC_WIDTH_L
-			0395 0038
-			//VSYNC_WIDTH_L
-			0396 0008
+			//HSYNC_WIDTH_L	HSYNC=40
+			0395 0028
+			//VSYNC_WIDTH_L	VSYNC=20
+			0396 0014
 			//HSYNC_WIDTH_H/VSYNC_WIDTH_H
 			0397 0000
-			//VFP_L
-			03B1 00C8
+			//VFP_L	 VFP=15
+			03B1 000F
 			//VBP_H
 			03B3 0000
-			//VFP_H/VBP_L
-			03B2 0020
-			//VRES_L
-			03B4 00D0
+			//VFP_H/VBP_L	VBP=10
+			03B2 000A
+			//VRES_L VRES=0X0438=1080
+			03B4 0038
 			//VRES_H
-			03B5 0002
-			//HFP_L
-			03B6 0038
+			03B5 0004
+			//HFP_L	 HFP=140
+			03B6 008C
 			//HBP_H
-			03B8 0002
-			//HFP_H/HBP_L
-			03B7 0000
-			//HRES_L
+			03B8 0006
+			//HFP_H/HBP_L	HBP=100
+			03B7 0004
+			//HRES_L HRES=0X0780=1920
 			03B9 0080
 			//HRES_H
 			03BA 0007
@@ -870,15 +870,15 @@
 			panel-size= <346 194>;
 
 			panel-timing {
-				clock-frequency = <115200000>;
+				clock-frequency = <148500000>;
 				hactive = <1920>;
-				vactive = <720>;
-				hfront-porch = <56>;
-				hsync-len = <32>;
-				hback-porch = <56>;
-				vfront-porch = <200>;
-				vsync-len = <2>;
-				vback-porch = <8>;
+				vactive = <1080>;
+				hfront-porch = <140>;
+				hsync-len = <40>;
+				hback-porch = <100>;
+				vfront-porch = <15>;
+				vsync-len = <20>;
+				vback-porch = <10>;
 				hsync-active = <0>;
 				vsync-active = <0>;
 				de-active = <0>;
@@ -2434,5 +2434,5 @@
 
 &vp3 {
 	assigned-clocks = <&cru DCLK_VOP3>;
-	assigned-clock-parents = <&cru PLL_V0PLL>;
+	assigned-clock-parents = <&cru PLL_GPLL>;
 };