From d1478aea649e739a0a0e4890cd8b049ae5d08c13 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 29 Jun 2023 18:01:32 +0200 Subject: [PATCH 01/11] memory: tegra: Add dummy implementation on Tegra194 With the introduction of commit 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234"), the PCI driver on Tegra194 and later requires an interconnect provider. However, a provider is currently only exposed on Tegra234 and this causes PCI on Tegra194 to defer probe indefinitely. Fix this by adding a dummy implementation on Tegra194. This allows nodes to be provided to interconnect consumers, but doesn't do any bandwidth accounting or frequency scaling. Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234") Reported-by: Jon Hunter Signed-off-by: Thierry Reding Reviewed-by: Sumit Gupta Tested-by: Sumit Gupta Link: https://lore.kernel.org/r/20230629160132.768940-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 37 +++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 23 +------------------- include/soc/tegra/mc.h | 3 +++ 4 files changed, 42 insertions(+), 22 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 4a750da1c12a..deb6e65b59af 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -755,6 +755,43 @@ const char *const tegra_mc_error_names[8] = { [6] = "SMMU translation error", }; +struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id == spec->args[0]) + return node; + } + + /* + * If a client driver calls devm_of_icc_get() before the MC driver + * is probed, then return EPROBE_DEFER to the client driver. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak) +{ + *average = 0; + *peak = 0; + + return 0; +} + +static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +const struct tegra_mc_icc_ops tegra_mc_icc_ops = { + .xlate = tegra_mc_icc_xlate, + .aggregate = icc_std_aggregate, + .get_bw = tegra_mc_icc_get, + .set = tegra_mc_icc_set, +}; + /* * Memory Controller (MC) has few Memory Clients that are issuing memory * bandwidth allocation requests to the MC interconnect provider. The MC diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index b2416ee3ac26..26035ac3a1eb 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1355,6 +1355,7 @@ const struct tegra_mc_soc tegra194_mc_soc = { MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .icc_ops = &tegra_mc_icc_ops, .ch_intmask = 0x00000f00, .global_intstatus_channel_shift = 8, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 8e873a7bc34f..4469430aa5fb 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -889,27 +889,6 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, return 0; } -static struct icc_node* -tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data) -{ - struct tegra_mc *mc = icc_provider_to_tegra_mc(data); - unsigned int cl_id = spec->args[0]; - struct icc_node *node; - - list_for_each_entry(node, &mc->provider.nodes, node_list) { - if (node->id != cl_id) - continue; - - return node; - } - - /* - * If a client driver calls devm_of_icc_get() before the MC driver - * is probed, then return EPROBE_DEFER to the client driver. - */ - return ERR_PTR(-EPROBE_DEFER); -} - static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) { *avg = 0; @@ -919,7 +898,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea } static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { - .xlate = tegra234_mc_of_icc_xlate, + .xlate = tegra_mc_icc_xlate, .aggregate = tegra234_mc_icc_aggregate, .get_bw = tegra234_mc_icc_get_init_bw, .set = tegra234_mc_icc_set, diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index fc3001483e62..a5ef84944a06 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -175,6 +175,9 @@ struct tegra_mc_icc_ops { int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak); }; +struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data); +extern const struct tegra_mc_icc_ops tegra_mc_icc_ops; + struct tegra_mc_ops { /* * @probe: Callback to set up SoC-specific bits of the memory controller. This is called From faafd6ca7e6e7100d21d3f43ec17674f36c9f843 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:14:00 +0530 Subject: [PATCH 02/11] memory: tegra: make icc_set_bw return zero if BWMGR not supported Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT is not supported by the BPMP-FW. Currently, 'EINVAL' is returned which causes error message in client drivers even when the platform doesn't support scaling. Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234") Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-5-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 4469430aa5fb..8fb83b39f5f5 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -827,7 +827,7 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) return 0; if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; if (!mc->bpmp) { dev_err(mc->dev, "BPMP reference NULL\n"); @@ -874,7 +874,7 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, struct tegra_mc *mc = icc_provider_to_tegra_mc(p); if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || From 6d0c4aa516280c3bab82cd3c53d142401eccab26 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:57 +0530 Subject: [PATCH 03/11] memory: tegra: sort tegra234_mc_clients table as per register offsets Sort the MC client entries in "tegra234_mc_clients" table as per the override and security register offsets. This will help to avoid creating duplicate entries. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-2-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 524 ++++++++++++++++---------------- 1 file changed, 264 insertions(+), 260 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 8fb83b39f5f5..84f4d964d834 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -12,6 +12,10 @@ #include #include "mc.h" +/* + * MC Client entries are sorted in the increasing order of the + * override and security register offsets. + */ static const struct tegra_mc_client tegra234_mc_clients[] = { { .id = TEGRA234_MEMORY_CLIENT_HDAR, @@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name = "pcie6ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x140, + .security = 0x144, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name = "pcie6aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x148, + .security = 0x14c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name = "pcie7ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x150, + .security = 0x154, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x160, + .security = 0x164, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x168, + .security = 0x16c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x170, + .security = 0x174, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x178, + .security = 0x17c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name = "pcie7aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x180, + .security = 0x184, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name = "pcie8ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x190, + .security = 0x194, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_HDAW, .name = "hdaw", @@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x1ac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name = "pcie8aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x1d8, + .security = 0x1dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name = "pcie9ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1e0, + .security = 0x1e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name = "pcie6ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name = "pcie9aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1f0, + .security = 0x1f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name = "pcie10ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x1f8, + .security = 0x1fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name = "pcie10aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x200, + .security = 0x204, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name = "pcie10ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x240, + .security = 0x244, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name = "pcie7ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x248, + .security = 0x24c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", @@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x370, + .security = 0x374, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x378, + .security = 0x37c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_VI2W, .name = "vi2w", @@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_VI2FALW, - .name = "vi2falw", - .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, - .type = TEGRA_ICC_ISO_VIFAL, - .sid = TEGRA234_SID_ISO_VI2FALC, - .regs = { - .sid = { - .override = 0x3e0, - .security = 0x3e4, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -217,6 +425,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x3dc, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALW, + .name = "vi2falw", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x3e0, + .security = 0x3e4, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", @@ -229,18 +449,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x494, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, - .name = "nvdisplayr1", - .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, - .type = TEGRA_ICC_ISO_DISPLAY, - .sid = TEGRA234_SID_ISO_NVDISPLAY, - .regs = { - .sid = { - .override = 0x508, - .security = 0x50c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_BPMPR, .name = "bpmpr", @@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x504, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDA, .name = "dla0rda", @@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x604, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x160, - .security = 0x164, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x748, - .security = 0x74c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB, .name = "dla0falwrb", @@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x60c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x168, - .security = 0x16c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x170, - .security = 0x174, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDA, .name = "dla0rda", @@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x624, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x178, - .security = 0x17c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x750, - .security = 0x754, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB, .name = "dla0falwrb", @@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x62c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x370, - .security = 0x374, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x378, - .security = 0x37c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE0R, .name = "pcie0r", @@ -609,6 +749,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x71c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x748, + .security = 0x74c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x750, + .security = 0x754, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, .name = "pcie5r1", @@ -621,162 +781,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x77c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, - .name = "pcie6ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x140, - .security = 0x144, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, - .name = "pcie6aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x148, - .security = 0x14c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, - .name = "pcie6ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x1e8, - .security = 0x1ec, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, - .name = "pcie7ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x150, - .security = 0x154, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, - .name = "pcie7aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x180, - .security = 0x184, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, - .name = "pcie7ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x248, - .security = 0x24c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, - .name = "pcie8ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x190, - .security = 0x194, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, - .name = "pcie8aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x1d8, - .security = 0x1dc, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, - .name = "pcie9ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1e0, - .security = 0x1e4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, - .name = "pcie9aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1f0, - .security = 0x1f4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, - .name = "pcie10ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x1f8, - .security = 0x1fc, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, - .name = "pcie10aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x200, - .security = 0x204, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, - .name = "pcie10ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x240, - .security = 0x244, - }, - }, }, { .id = TEGRA_ICC_MC_CPU_CLUSTER0, .name = "sw_cluster0", From b18e525990acb67f214f6b2528fae292ac9cf641 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:58 +0530 Subject: [PATCH 04/11] memory: tegra: Add clients used by DRM in Tegra234 Add entries for VIC, NVDEC, NVENC, NVJPG memory controller clients into the 'tegra_234_mc_clients' table. Signed-off-by: Johnny Liu Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-3-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 84f4d964d834..7954f339ca79 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -29,6 +29,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name = "nvencsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0xe0, + .security = 0xe4, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, .name = "pcie6ar", @@ -65,6 +77,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x154, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name = "nvencswr", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0x158, + .security = 0x15c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, .name = "dla0rdb", @@ -357,6 +381,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSRD, + .name = "vicsrd", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x360, + .security = 0x364, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSWR, + .name = "vicswr", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x368, + .security = 0x36c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, .name = "dla0rdb1", @@ -401,6 +449,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name = "nvdecsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name = "nvdecswr", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -437,6 +509,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x3e4, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD, + .name = "nvjpgsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR, + .name = "nvjpgswr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f8, + .security = 0x3fc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", @@ -781,6 +877,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x77c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD, + .name = "nvjpg1srd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x918, + .security = 0x91c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR, + .name = "nvjpg1swr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x920, + .security = 0x924, + }, + }, }, { .id = TEGRA_ICC_MC_CPU_CLUSTER0, .name = "sw_cluster0", From 0a7e4578567a3270ba35ebde4e0ce2795fa55384 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:59 +0530 Subject: [PATCH 05/11] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the BPMP-FW before making the MRQ request. Currently, if the BPMP-FW doesn't support this MRQ, then the "tegra186_emc_probe" fails. Due to this the Memory Interconnect initialization also doesn't happen. Memory Interconnect is not dependent on this MRQ and can initialize even when this MRQ is not supported in any platform. The check ensures that the MRQ is called only when it is supported by the BPMP-FW and Interconnect initializes independent of this MRQ. Also, moved the code to new function for better readability. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-4-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra186-emc.c | 136 +++++++++++++++------------- 1 file changed, 71 insertions(+), 65 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 6ad8a4023dd7..83981ae3ea86 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); +static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) +{ + struct mrq_emc_dvfs_latency_response response; + struct tegra_bpmp_message msg; + unsigned int i; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_EMC_DVFS_LATENCY; + msg.tx.data = NULL; + msg.tx.size = 0; + msg.rx.data = &response; + msg.rx.size = sizeof(response); + + err = tegra_bpmp_transfer(emc->bpmp, &msg); + if (err < 0) { + dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err); + return err; + } + if (msg.rx.ret < 0) { + dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); + return -EINVAL; + } + + emc->debugfs.min_rate = ULONG_MAX; + emc->debugfs.max_rate = 0; + + emc->num_dvfs = response.num_pairs; + + emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL); + if (!emc->dvfs) + return -ENOMEM; + + dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs); + + for (i = 0; i < emc->num_dvfs; i++) { + emc->dvfs[i].rate = response.pairs[i].freq * 1000; + emc->dvfs[i].latency = response.pairs[i].latency; + + if (emc->dvfs[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->dvfs[i].rate; + + if (emc->dvfs[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->dvfs[i].rate; + + dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i, + emc->dvfs[i].rate, emc->dvfs[i].latency); + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate); + if (err < 0) { + dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n", + emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk); + return err; + } + + emc->debugfs.root = debugfs_create_dir("emc", NULL); + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, + emc, &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_max_rate_fops); + + return 0; +} + /* * tegra_emc_icc_set_bw() - Set BW api for EMC provider * @src: ICC node for External Memory Controller (EMC) @@ -251,10 +318,7 @@ err_msg: static int tegra186_emc_probe(struct platform_device *pdev) { struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); - struct mrq_emc_dvfs_latency_response response; - struct tegra_bpmp_message msg; struct tegra186_emc *emc; - unsigned int i; int err; emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); @@ -275,69 +339,11 @@ static int tegra186_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); emc->dev = &pdev->dev; - memset(&msg, 0, sizeof(msg)); - msg.mrq = MRQ_EMC_DVFS_LATENCY; - msg.tx.data = NULL; - msg.tx.size = 0; - msg.rx.data = &response; - msg.rx.size = sizeof(response); - - err = tegra_bpmp_transfer(emc->bpmp, &msg); - if (err < 0) { - dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); - goto put_bpmp; + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { + err = tegra186_emc_get_emc_dvfs_latency(emc); + if (err) + goto put_bpmp; } - if (msg.rx.ret < 0) { - err = -EINVAL; - dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); - goto put_bpmp; - } - - emc->debugfs.min_rate = ULONG_MAX; - emc->debugfs.max_rate = 0; - - emc->num_dvfs = response.num_pairs; - - emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, - sizeof(*emc->dvfs), GFP_KERNEL); - if (!emc->dvfs) { - err = -ENOMEM; - goto put_bpmp; - } - - dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); - - for (i = 0; i < emc->num_dvfs; i++) { - emc->dvfs[i].rate = response.pairs[i].freq * 1000; - emc->dvfs[i].latency = response.pairs[i].latency; - - if (emc->dvfs[i].rate < emc->debugfs.min_rate) - emc->debugfs.min_rate = emc->dvfs[i].rate; - - if (emc->dvfs[i].rate > emc->debugfs.max_rate) - emc->debugfs.max_rate = emc->dvfs[i].rate; - - dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, - emc->dvfs[i].rate, emc->dvfs[i].latency); - } - - err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, - emc->debugfs.max_rate); - if (err < 0) { - dev_err(&pdev->dev, - "failed to set rate range [%lu-%lu] for %pC\n", - emc->debugfs.min_rate, emc->debugfs.max_rate, - emc->clk); - goto put_bpmp; - } - - emc->debugfs.root = debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); if (mc && mc->soc->icc_ops) { if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { From 6e1547f9873b0cea840625081ee4e5d7dd26661a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 14 Jul 2023 17:01:16 +0200 Subject: [PATCH 06/11] memory: tegra: Prefer octal over symbolic permissions checkpatch recommends using octal permissions instead of symbolic permissions. Switch the debugfs files to use the former to silence these warnings. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20230714150116.2823766-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra186-emc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 83981ae3ea86..4007f4e16d74 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -212,12 +212,12 @@ static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) } emc->debugfs.root = debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); + debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, + &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc, + &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc, + &tegra186_emc_debug_max_rate_fops); return 0; } From 0b4838717fff5e24d97742e79ba1ee46cbfbf4b6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:47:16 -0600 Subject: [PATCH 07/11] memory: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714174717.4059518-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/brcmstb_dpfe.c | 3 +-- drivers/memory/da8xx-ddrctl.c | 1 - drivers/memory/fsl_ifc.c | 2 +- drivers/memory/jz4780-nemc.c | 1 - drivers/memory/pl353-smc.c | 1 + drivers/memory/renesas-rpc-if.c | 1 - drivers/memory/samsung/exynos5422-dmc.c | 2 +- drivers/memory/stm32-fmc2-ebi.c | 2 ++ drivers/memory/tegra/mc.c | 2 +- drivers/memory/tegra/tegra124.c | 2 +- drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra20.c | 3 ++- drivers/memory/tegra/tegra210-emc-core.c | 4 ++-- drivers/memory/tegra/tegra30-emc.c | 2 +- drivers/memory/tegra/tegra30.c | 2 +- 15 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c index 9339f80b21c5..a7ab3d377206 100644 --- a/drivers/memory/brcmstb_dpfe.c +++ b/drivers/memory/brcmstb_dpfe.c @@ -32,8 +32,7 @@ #include #include #include -#include -#include +#include #include #define DRVNAME "brcmstb-dpfe" diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c index 0ef8cc878b95..2bf34da85d22 100644 --- a/drivers/memory/da8xx-ddrctl.c +++ b/drivers/memory/da8xx-ddrctl.c @@ -10,7 +10,6 @@ #include #include -#include #include #include diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c index 9e8d8e9c5ad8..2509e5152036 100644 --- a/drivers/memory/fsl_ifc.c +++ b/drivers/memory/fsl_ifc.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index 555f7ac3b7dd..e5a93e7da15f 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c index d39ee7d06665..48540817e046 100644 --- a/drivers/memory/pl353-smc.c +++ b/drivers/memory/pl353-smc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 75fcba45ec1b..9695b2d3ae59 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index c491cd549644..6d019dbd721c 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index ffec26a99313..9015e8277dc8 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include #include diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index deb6e65b59af..67d6e70b4eab 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index d780a84241fe..470b7dbab2c2 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 7bb73f06fad3..533f85a4b2bd 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -7,7 +7,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index fcd7738fcb53..544bfd216a22 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -5,8 +5,9 @@ #include #include +#include #include -#include +#include #include #include diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index ae5f982f861b..3300bde47c13 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -9,10 +9,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index c91e9b7e2e01..9eae25c57ec6 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 84316357513d..06f8b35e0a14 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -3,8 +3,8 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ +#include #include -#include #include #include From eb6bb73f5762cd4eb1eadc42a357f8f13b0f37ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:46 +0200 Subject: [PATCH 08/11] dt-bindings: memory-controllers: ingenic,nemc: reference peripheral properties Ingenic NAND / External Memory Controller has children with peripheral properties, so it should reference the Memory Controller bus Peripheral-specific schema. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/ingenic,nemc.yaml | 1 + .../bindings/memory-controllers/mc-peripheral-props.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml index a02724221ff3..b40cec0eb651 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml @@ -39,6 +39,7 @@ properties: patternProperties: ".*@[0-9]+$": type: object + $ref: mc-peripheral-props.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 5acfcad12bb7..5ff8cc26962a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -34,6 +34,7 @@ required: # The controller specific properties go here. allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# + - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# additionalProperties: true From a98dcaaa019996e52244feee54a043ddfb4050cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:47 +0200 Subject: [PATCH 09/11] dt-bindings: memory-controllers: reference TI GPMC peripheral properties Reference the Texas Instruments GPMC Bus Child Nodes schema with peripheral properties, in common Memory Controller bus Peripheral-specific schema, to allow properly validate devices like davicom,dm9000. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/mc-peripheral-props.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 5ff8cc26962a..8d9dae15ade0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -36,5 +36,6 @@ allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# + - $ref: ti,gpmc-child.yaml# additionalProperties: true From f7812cdabb82b2b143bba7cb1736889cd56d2092 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:48 +0200 Subject: [PATCH 10/11] dt-bindings: net: davicom,dm9000: convert to DT schema Convert the Davicom DM9000 Fast Ethernet Controller bindings to DT schema. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/net/davicom,dm9000.yaml | 59 +++++++++++++++++++ .../bindings/net/davicom-dm9000.txt | 27 --------- 2 files changed, 59 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9000.yaml delete mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt diff --git a/Documentation/devicetree/bindings/net/davicom,dm9000.yaml b/Documentation/devicetree/bindings/net/davicom,dm9000.yaml new file mode 100644 index 000000000000..66a7c6eec767 --- /dev/null +++ b/Documentation/devicetree/bindings/net/davicom,dm9000.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/davicom,dm9000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Davicom DM9000 Fast Ethernet Controller + +maintainers: + - Paul Cercueil + +properties: + compatible: + const: davicom,dm9000 + + reg: + items: + - description: Address registers + - description: Data registers + + interrupts: + maxItems: 1 + + davicom,no-eeprom: + type: boolean + description: Configuration EEPROM is not available + + davicom,ext-phy: + type: boolean + description: Use external PHY + + reset-gpios: + maxItems: 1 + + vcc-supply: true + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + - $ref: /schemas/net/ethernet-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@a8000000 { + compatible = "davicom,dm9000"; + reg = <0xa8000000 0x2>, <0xa8000002 0x2>; + interrupt-parent = <&gph1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + local-mac-address = [00 00 de ad be ef]; + davicom,no-eeprom; + }; diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt deleted file mode 100644 index 64c159e9cbf7..000000000000 --- a/Documentation/devicetree/bindings/net/davicom-dm9000.txt +++ /dev/null @@ -1,27 +0,0 @@ -Davicom DM9000 Fast Ethernet controller - -Required properties: -- compatible = "davicom,dm9000"; -- reg : physical addresses and sizes of registers, must contain 2 entries: - first entry : address register, - second entry : data register. -- interrupts : interrupt specifier specific to interrupt controller - -Optional properties: -- davicom,no-eeprom : Configuration EEPROM is not available -- davicom,ext-phy : Use external PHY -- reset-gpios : phandle of gpio that will be used to reset chip during probe -- vcc-supply : phandle of regulator that will be used to enable power to chip - -Example: - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 4>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>; - vcc-supply = <ð0_power>; - }; From 35bd78cf252245f11dd1c9d5f1b414c25e727b5a Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 1 Aug 2023 17:40:23 +0530 Subject: [PATCH 11/11] memory: tegra: add MC client for Tegra234 GPU Add the Non-ISO MC client for the Tegra234 GPU to the tegra234_mc_clients table. Signed-off-by: Sumit Gupta Link: https://lore.kernel.org/r/20230801121023.27841-1-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 7954f339ca79..9e5b5dbd9c8d 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -916,6 +916,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .name = "sw_cluster2", .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2, .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVL1R, + .name = "nvl1r", + .bpmp_id = TEGRA_ICC_BPMP_GPU, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVL1W, + .name = "nvl1w", + .bpmp_id = TEGRA_ICC_BPMP_GPU, + .type = TEGRA_ICC_NISO, }, };