diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-edp.c b/drivers/phy/rockchip/phy-rockchip-naneng-edp.c index b0ba5867f4db..209ce9d0384a 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-edp.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-edp.c @@ -5,6 +5,7 @@ * Author: Wyon Bi */ +#include #include #include #include @@ -14,67 +15,74 @@ #include #include #include -#include +#include +#include #include -#define HIWORD_UPDATE(x, h, l) ((((x) << (l)) & GENMASK((h), (l))) | \ - (GENMASK((h), (l)) << 16)) - #define EDP_PHY_GRF_CON0 0x0000 -#define EDP_PHY_TX_IDLE(x) HIWORD_UPDATE(x, 11, 8) -#define EDP_PHY_TX_PD(x) HIWORD_UPDATE(x, 7, 4) -#define EDP_PHY_IDDQ_EN(x) HIWORD_UPDATE(x, 1, 1) -#define EDP_PHY_PD_PLL(x) HIWORD_UPDATE(x, 0, 0) +#define EDP_PHY_TX_IDLE GENMASK(11, 8) +#define EDP_PHY_TX_PD GENMASK(7, 4) +#define EDP_PHY_IDDQ_EN BIT(1) +#define EDP_PHY_PD_PLL BIT(0) #define EDP_PHY_GRF_CON1 0x0004 -#define EDP_PHY_PLL_DIV(x) HIWORD_UPDATE(x, 14, 0) +#define EDP_PHY_PLL_DIV GENMASK(14, 0) #define EDP_PHY_GRF_CON2 0x0008 -#define EDP_PHY_TX_RTERM(x) HIWORD_UPDATE(x, 10, 8) -#define EDP_PHY_RATE(x) HIWORD_UPDATE(x, 5, 4) -#define EDP_PHY_REF_DIV(x) HIWORD_UPDATE(x, 3, 0) +#define EDP_PHY_TX_RTERM GENMASK(10, 8) +#define EDP_PHY_RATE GENMASK(5, 4) +#define EDP_PHY_REF_DIV GENMASK(3, 0) #define EDP_PHY_GRF_CON3 0x000c -#define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, \ - 4 * (lane)) +#define EDP_PHY_TX3_EMP GENMASK(15, 12) +#define EDP_PHY_TX2_EMP GENMASK(11, 8) +#define EDP_PHY_TX1_EMP GENMASK(7, 4) +#define EDP_PHY_TX0_EMP GENMASK(3, 0) #define EDP_PHY_GRF_CON4 0x0010 -#define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, \ - 4 * (lane)) +#define EDP_PHY_TX3_AMP GENMASK(14, 12) +#define EDP_PHY_TX2_AMP GENMASK(10, 8) +#define EDP_PHY_TX1_AMP GENMASK(6, 4) +#define EDP_PHY_TX0_AMP GENMASK(2, 0) #define EDP_PHY_GRF_CON5 0x0014 -#define EDP_PHY_TX_MODE(x) HIWORD_UPDATE(x, 9, 8) -#define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, \ - 2 * (lane)) +#define EDP_PHY_TX_MODE GENMASK(9, 8) +#define EDP_PHY_TX3_AMP_SCALE GENMASK(7, 6) +#define EDP_PHY_TX2_AMP_SCALE GENMASK(5, 4) +#define EDP_PHY_TX1_AMP_SCALE GENMASK(3, 2) +#define EDP_PHY_TX0_AMP_SCALE GENMASK(1, 0) #define EDP_PHY_GRF_CON6 0x0018 -#define EDP_PHY_SSC_DEPTH(x) HIWORD_UPDATE(x, 15, 12) -#define EDP_PHY_SSC_EN(x) HIWORD_UPDATE(x, 11, 11) -#define EDP_PHY_SSC_CNT(x) HIWORD_UPDATE(x, 9, 0) +#define EDP_PHY_SSC_DEPTH GENMASK(15, 12) +#define EDP_PHY_SSC_EN BIT(11) +#define EDP_PHY_SSC_CNT GENMASK(9, 0) #define EDP_PHY_GRF_CON7 0x001c #define EDP_PHY_GRF_CON8 0x0020 -#define EDP_PHY_PLL_CTL_H(x) HIWORD_UPDATE(x, 15, 0) +#define EDP_PHY_PLL_CTL_H GENMASK(15, 0) #define EDP_PHY_GRF_CON9 0x0024 -#define EDP_PHY_TX_CTL(x) HIWORD_UPDATE(x, 15, 0) +#define EDP_PHY_TX_CTL GENMASK(15, 0) #define EDP_PHY_GRF_CON10 0x0028 -#define EDP_PHY_AUX_RCV_PD_SEL(x) HIWORD_UPDATE(x, 5, 5) -#define EDP_PHY_AUX_DRV_PD_SEL(x) HIWORD_UPDATE(x, 4, 4) -#define EDP_PHY_AUX_IDLE_MASK BIT(2) -#define EDP_PHY_AUX_IDLE(x) HIWORD_UPDATE(x, 2, 2) -#define EDP_PHY_AUX_RCV_PD(x) HIWORD_UPDATE(x, 1, 1) -#define EDP_PHY_AUX_DRV_PD(x) HIWORD_UPDATE(x, 0, 0) +#define EDP_PHY_AUX_RCV_PD_SEL BIT(5) +#define EDP_PHY_AUX_DRV_PD_SEL BIT(4) +#define EDP_PHY_AUX_IDLE BIT(2) +#define EDP_PHY_AUX_RCV_PD BIT(1) +#define EDP_PHY_AUX_DRV_PD BIT(0) #define EDP_PHY_GRF_CON11 0x002c -#define EDP_PHY_AUX_RCV_VCM(x) HIWORD_UPDATE(x, 14, 12) -#define EDP_PHY_AUX_MODE(x) HIWORD_UPDATE(x, 11, 10) -#define EDP_PHY_AUX_AMP_SCALE(x) HIWORD_UPDATE(x, 9, 8) -#define EDP_PHY_AUX_AMP(x) HIWORD_UPDATE(x, 6, 4) -#define EDP_PHY_AUX_RTERM(x) HIWORD_UPDATE(x, 2, 0) +#define EDP_PHY_AUX_RCV_VCM GENMASK(14, 12) +#define EDP_PHY_AUX_MODE GENMASK(11, 10) +#define EDP_PHY_AUX_AMP_SCALE GENMASK(9, 8) +#define EDP_PHY_AUX_AMP GENMASK(6, 4) +#define EDP_PHY_AUX_RTERM GENMASK(2, 0) #define EDP_PHY_GRF_STATUS0 0x0030 #define PLL_RDY BIT(0) #define EDP_PHY_GRF_STATUS1 0x0034 struct rockchip_edp_phy { - void __iomem *regs; + struct regmap *grf; struct device *dev; - struct clk *pclk; struct clk *refclk; - struct reset_control *apb_reset; }; +static inline int rockchip_grf_write(struct regmap *grf, unsigned int reg, + unsigned int mask, unsigned int val) +{ + return regmap_write(grf, reg, (mask << 16) | (val & mask)); +} + static struct { int amp; int amp_scale; @@ -86,25 +94,71 @@ static struct { { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} }, }; +static void rockchip_edp_phy_set_voltage(struct rockchip_edp_phy *edpphy, + struct phy_configure_opts_dp *dp, + u8 lane) +{ + u32 amp, amp_scale, emp; + + amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; + amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; + emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; + + switch (lane) { + case 0: + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, + EDP_PHY_TX0_EMP, + FIELD_PREP(EDP_PHY_TX0_EMP, emp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, + EDP_PHY_TX0_AMP, + FIELD_PREP(EDP_PHY_TX0_AMP, amp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, + EDP_PHY_TX0_AMP_SCALE, + FIELD_PREP(EDP_PHY_TX0_AMP_SCALE, amp_scale)); + break; + case 1: + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, + EDP_PHY_TX1_EMP, + FIELD_PREP(EDP_PHY_TX1_EMP, emp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, + EDP_PHY_TX1_AMP, + FIELD_PREP(EDP_PHY_TX1_AMP, amp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, + EDP_PHY_TX1_AMP_SCALE, + FIELD_PREP(EDP_PHY_TX1_AMP_SCALE, amp_scale)); + break; + case 2: + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, + EDP_PHY_TX2_EMP, + FIELD_PREP(EDP_PHY_TX2_EMP, emp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, + EDP_PHY_TX2_AMP, + FIELD_PREP(EDP_PHY_TX2_AMP, amp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, + EDP_PHY_TX2_AMP_SCALE, + FIELD_PREP(EDP_PHY_TX2_AMP_SCALE, amp_scale)); + break; + case 3: + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, + EDP_PHY_TX3_EMP, + FIELD_PREP(EDP_PHY_TX3_EMP, emp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, + EDP_PHY_TX3_AMP, + FIELD_PREP(EDP_PHY_TX3_AMP, amp)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, + EDP_PHY_TX3_AMP_SCALE, + FIELD_PREP(EDP_PHY_TX3_AMP_SCALE, amp_scale)); + break; + } +} + static int rockchip_edp_phy_set_voltages(struct rockchip_edp_phy *edpphy, struct phy_configure_opts_dp *dp) { u8 lane; - u32 val; - for (lane = 0; lane < dp->lanes; lane++) { - val = vp[dp->voltage[lane]][dp->pre[lane]].amp; - writel(EDP_PHY_TX_AMP(lane, val), - edpphy->regs + EDP_PHY_GRF_CON4); - - val = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; - writel(EDP_PHY_TX_AMP_SCALE(lane, val), - edpphy->regs + EDP_PHY_GRF_CON5); - - val = vp[dp->voltage[lane]][dp->pre[lane]].emp; - writel(EDP_PHY_TX_EMP(lane, val), - edpphy->regs + EDP_PHY_GRF_CON3); - } + for (lane = 0; lane < dp->lanes; lane++) + rockchip_edp_phy_set_voltage(edpphy, dp, lane); return 0; } @@ -115,53 +169,77 @@ static int rockchip_edp_phy_set_rate(struct rockchip_edp_phy *edpphy, u32 value; int ret; - writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf), - edpphy->regs + EDP_PHY_GRF_CON0); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, + EDP_PHY_TX_IDLE | EDP_PHY_TX_PD, + FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) | + FIELD_PREP(EDP_PHY_TX_PD, 0xf)); usleep_range(100, 101); - writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5); - writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, + FIELD_PREP(EDP_PHY_TX_MODE, 0x3)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, + FIELD_PREP(EDP_PHY_PD_PLL, 0x1)); switch (dp->link_rate) { case 1620: - writel(EDP_PHY_PLL_DIV(0x4380), - edpphy->regs + EDP_PHY_GRF_CON1); - writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x1) | - EDP_PHY_REF_DIV(0x0), edpphy->regs + EDP_PHY_GRF_CON2); - writel(EDP_PHY_PLL_CTL_H(0x0800), - edpphy->regs + EDP_PHY_GRF_CON8); - writel(EDP_PHY_TX_CTL(0x0000), edpphy->regs + EDP_PHY_GRF_CON9); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, + EDP_PHY_PLL_DIV, + FIELD_PREP(EDP_PHY_PLL_DIV, 0x4380)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, + EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV, + FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) | + FIELD_PREP(EDP_PHY_RATE, 0x1) | + FIELD_PREP(EDP_PHY_REF_DIV, 0x0)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, + EDP_PHY_PLL_CTL_H, + FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, + EDP_PHY_TX_CTL, + FIELD_PREP(EDP_PHY_TX_CTL, 0x0000)); break; case 2700: - writel(EDP_PHY_PLL_DIV(0x3840), - edpphy->regs + EDP_PHY_GRF_CON1); - writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x0) | - EDP_PHY_REF_DIV(0x0), edpphy->regs + EDP_PHY_GRF_CON2); - writel(EDP_PHY_PLL_CTL_H(0x0800), - edpphy->regs + EDP_PHY_GRF_CON8); - writel(EDP_PHY_TX_CTL(0x0000), edpphy->regs + EDP_PHY_GRF_CON9); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, + EDP_PHY_PLL_DIV, + FIELD_PREP(EDP_PHY_PLL_DIV, 0x3840)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, + EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV, + FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) | + FIELD_PREP(EDP_PHY_RATE, 0x0) | + FIELD_PREP(EDP_PHY_REF_DIV, 0x0)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, + EDP_PHY_PLL_CTL_H, + FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, + EDP_PHY_TX_CTL, + FIELD_PREP(EDP_PHY_TX_CTL, 0x0000)); break; } if (dp->ssc) - writel(EDP_PHY_SSC_DEPTH(0x9) | EDP_PHY_SSC_EN(0x1) | - EDP_PHY_SSC_CNT(0x17d), - edpphy->regs + EDP_PHY_GRF_CON6); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, + EDP_PHY_SSC_DEPTH | EDP_PHY_SSC_EN | EDP_PHY_SSC_CNT, + FIELD_PREP(EDP_PHY_SSC_DEPTH, 0x9) | + FIELD_PREP(EDP_PHY_SSC_EN, 0x1) | + FIELD_PREP(EDP_PHY_SSC_CNT, 0x17d)); else - writel(EDP_PHY_SSC_EN(0x0), edpphy->regs + EDP_PHY_GRF_CON6); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, + EDP_PHY_SSC_EN, + FIELD_PREP(EDP_PHY_SSC_EN, 0x0)); - writel(EDP_PHY_PD_PLL(0x0), edpphy->regs + EDP_PHY_GRF_CON0); - writel(EDP_PHY_TX_PD(~GENMASK(dp->lanes - 1, 0)), - edpphy->regs + EDP_PHY_GRF_CON0); - ret = readl_poll_timeout(edpphy->regs + EDP_PHY_GRF_STATUS0, - value, value & PLL_RDY, 100, 1000); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, + FIELD_PREP(EDP_PHY_PD_PLL, 0)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_PD, + FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0))); + ret = regmap_read_poll_timeout(edpphy->grf, EDP_PHY_GRF_STATUS0, + value, value & PLL_RDY, 100, 1000); if (ret) { dev_err(edpphy->dev, "pll is not ready: %d\n", ret); return ret; } - writel(EDP_PHY_TX_MODE(0x0), edpphy->regs + EDP_PHY_GRF_CON5); - writel(EDP_PHY_TX_IDLE(~GENMASK(dp->lanes - 1, 0)), - edpphy->regs + EDP_PHY_GRF_CON0); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, + FIELD_PREP(EDP_PHY_TX_MODE, 0x0)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_IDLE, + FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0))); return 0; } @@ -253,44 +331,51 @@ static bool rockchip_edp_phy_enabled(struct rockchip_edp_phy *edpphy) { u32 val; - val = readl(edpphy->regs + EDP_PHY_GRF_CON10); + regmap_read(edpphy->grf, EDP_PHY_GRF_STATUS0, &val); - if (val & EDP_PHY_AUX_IDLE_MASK) - return false; - - return true; + return FIELD_GET(PLL_RDY, val); } static int rockchip_edp_phy_power_on(struct phy *phy) { struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); - clk_prepare_enable(edpphy->pclk); clk_prepare_enable(edpphy->refclk); if (rockchip_edp_phy_enabled(edpphy)) return 0; - reset_control_assert(edpphy->apb_reset); - usleep_range(100, 101); - reset_control_deassert(edpphy->apb_reset); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, + EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE, + FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) | + FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) | + FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, + EDP_PHY_TX_IDLE | EDP_PHY_TX_PD | EDP_PHY_PD_PLL, + FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) | + FIELD_PREP(EDP_PHY_TX_PD, 0xf) | + FIELD_PREP(EDP_PHY_PD_PLL, 0x1)); usleep_range(100, 101); - writel(EDP_PHY_AUX_RCV_PD(0x1) | EDP_PHY_AUX_DRV_PD(0x1) | - EDP_PHY_AUX_IDLE(0x1), edpphy->regs + EDP_PHY_GRF_CON10); - writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf) | EDP_PHY_PD_PLL(0x1), - edpphy->regs + EDP_PHY_GRF_CON0); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON11, + EDP_PHY_AUX_RCV_VCM | EDP_PHY_AUX_MODE | + EDP_PHY_AUX_AMP_SCALE | EDP_PHY_AUX_AMP | + EDP_PHY_AUX_RTERM, + FIELD_PREP(EDP_PHY_AUX_RCV_VCM, 0x4) | + FIELD_PREP(EDP_PHY_AUX_MODE, 0x1) | + FIELD_PREP(EDP_PHY_AUX_AMP_SCALE, 0x1) | + FIELD_PREP(EDP_PHY_AUX_AMP, 0x3) | + FIELD_PREP(EDP_PHY_AUX_RTERM, 0x1)); + + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, + EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD, + FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x0) | + FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x0)); usleep_range(100, 101); - writel(EDP_PHY_AUX_RCV_VCM(0x4) | EDP_PHY_AUX_MODE(0x1) | - EDP_PHY_AUX_AMP_SCALE(0x1) | EDP_PHY_AUX_AMP(0x3) | - EDP_PHY_AUX_RTERM(0x1), edpphy->regs + EDP_PHY_GRF_CON11); - - writel(EDP_PHY_AUX_RCV_PD(0x0) | EDP_PHY_AUX_DRV_PD(0x0), - edpphy->regs + EDP_PHY_GRF_CON10); - usleep_range(100, 101); - - writel(EDP_PHY_AUX_IDLE(0x0), edpphy->regs + EDP_PHY_GRF_CON10); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, + EDP_PHY_AUX_IDLE, + FIELD_PREP(EDP_PHY_AUX_IDLE, 0x0)); usleep_range(10000, 11000); return 0; @@ -300,16 +385,22 @@ static int rockchip_edp_phy_power_off(struct phy *phy) { struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); - writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf), - edpphy->regs + EDP_PHY_GRF_CON0); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, + EDP_PHY_TX_IDLE | EDP_PHY_TX_PD, + FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) | + FIELD_PREP(EDP_PHY_TX_PD, 0xf)); usleep_range(100, 101); - writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5); - writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0); - writel(EDP_PHY_AUX_RCV_PD(0x1) | EDP_PHY_AUX_DRV_PD(0x1) | - EDP_PHY_AUX_IDLE(0x1), edpphy->regs + EDP_PHY_GRF_CON10); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, + FIELD_PREP(EDP_PHY_TX_MODE, 0x3)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, + FIELD_PREP(EDP_PHY_PD_PLL, 0x1)); + rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, + EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE, + FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) | + FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) | + FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1)); clk_disable_unprepare(edpphy->refclk); - clk_disable_unprepare(edpphy->pclk); return 0; } @@ -327,7 +418,6 @@ static int rockchip_edp_phy_probe(struct platform_device *pdev) struct rockchip_edp_phy *edpphy; struct phy *phy; struct phy_provider *phy_provider; - struct resource *res; int ret; edpphy = devm_kzalloc(dev, sizeof(*edpphy), GFP_KERNEL); @@ -336,10 +426,12 @@ static int rockchip_edp_phy_probe(struct platform_device *pdev) edpphy->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - edpphy->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(edpphy->regs)) - return PTR_ERR(edpphy->regs); + edpphy->grf = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(edpphy->grf)) { + ret = PTR_ERR(edpphy->grf); + dev_err(dev, "failed to get grf: %d\n", ret); + return ret; + } edpphy->refclk = devm_clk_get(dev, "refclk"); if (IS_ERR(edpphy->refclk)) { @@ -348,20 +440,6 @@ static int rockchip_edp_phy_probe(struct platform_device *pdev) return ret; } - edpphy->pclk = devm_clk_get(dev, "pclk"); - if (IS_ERR(edpphy->pclk)) { - ret = PTR_ERR(edpphy->pclk); - dev_err(dev, "failed to get pclk: %d\n", ret); - return ret; - } - - edpphy->apb_reset = devm_reset_control_get(dev, "apb"); - if (IS_ERR(edpphy->apb_reset)) { - ret = PTR_ERR(edpphy->apb_reset); - dev_err(dev, "failed to get apb reset: %d\n", ret); - return ret; - } - phy = devm_phy_create(dev, NULL, &rockchip_edp_phy_ops); if (IS_ERR(phy)) { ret = PTR_ERR(phy);