From 3dc93ab5870000d50cad9625cf2b9035fc3d2d34 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 12 Sep 2024 15:08:21 +0000 Subject: [PATCH] Revert "spi: microchip-core: fix init function not setting the master and motorola modes" This reverts commit 99dab05987f82d036164444d3cd29daa796bdc1e which is commit 3a5e76283672efddf47cea39ccfe9f5735cc91d5 upstream. It breaks the Android kernel abi and can be brought back in the future in an abi-safe way if it is really needed. Bug: 161946584 Change-Id: I46d93ecc53d873a566f2d3ef8a9e8acf3a09cc59 Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-microchip-core.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index bfad0fe743ad..a5173d820ac2 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -289,13 +289,17 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi * unsigned long clk_hz; u32 control = mchp_corespi_read(spi, REG_CONTROL); - control &= ~CONTROL_ENABLE; - mchp_corespi_write(spi, REG_CONTROL, control); - control |= CONTROL_MASTER; + control &= ~CONTROL_MODE_MASK; control |= MOTOROLA_MODE; + mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); + + /* max. possible spi clock rate is the apb clock rate */ + clk_hz = clk_get_rate(spi->clk); + host->max_speed_hz = clk_hz; + /* * The controller must be configured so that it doesn't remove Chip * Select until the entire message has been transferred, even if at @@ -304,16 +308,11 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi * * BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames * for the 8 bit transfers that this driver uses. */ + control = mchp_corespi_read(spi, REG_CONTROL); control |= CONTROL_SPS | CONTROL_BIGFIFO; mchp_corespi_write(spi, REG_CONTROL, control); - mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); - - /* max. possible spi clock rate is the apb clock rate */ - clk_hz = clk_get_rate(spi->clk); - host->max_speed_hz = clk_hz; - mchp_corespi_enable_ints(spi); /*