From 3e176f1746ec681066649af0f9ab74edff79078d Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 1 Sep 2025 14:59:58 +0800 Subject: [PATCH] arm64: dts: rockchip: rv1126b: Add spec-sn for cpuinfo RV1126B: rockchip-cpuinfo cpuinfo: SoC : 1126xb01 RV1126B-P: rockchip-cpuinfo cpuinfo: SoC : 1126xb10 Note: * x: don't care. * bit[7~0]: 0x1 ~ 0x1a --- A ~ Z Signed-off-by: Sugar Zhang Change-Id: Ibe21215fd1829e19aea6070419ee565abf05ca97 --- arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi index 3cc7792d19c3..84b8db03c024 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi @@ -405,8 +405,8 @@ cpuinfo { compatible = "rockchip,cpuinfo"; - nvmem-cells = <&otp_id>, <&cpu_version>, <&cpu_code>; - nvmem-cell-names = "id", "cpu-version", "cpu-code"; + nvmem-cells = <&otp_id>, <&cpu_version>, <&cpu_code>, <&specification_serial_number>; + nvmem-cell-names = "id", "cpu-version", "cpu-code", "spec-sn"; }; /* dphy0 full mode */ @@ -1942,7 +1942,7 @@ cpu_code: cpu-code@2 { reg = <0x02 0x2>; }; - specification_serial_number: specification-serial-number@7 { + specification_serial_number: specification-serial-number@8 { reg = <0x08 0x1>; bits = <0 5>; };