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clk: rockchip: optimizing ddrclk_scpi_recalc_rate behavior

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Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to
rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce
SCPI APIs usage rate.

Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping
2017-04-06 15:25:12 +08:00
committed by Huang, Tao
parent 6168e92bdd
commit 3e61936275
1 changed files with 13 additions and 1 deletions
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14
drivers/clk/rockchip/clk-ddr.c
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@@ -105,6 +105,8 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
.get_parent = rockchip_ddrclk_get_parent,
};
static u32 ddr_clk_cached;
static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
@@ -112,6 +114,13 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
u32 lcdc_type = 7;
ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
if (ret) {
ddr_clk_cached = ret;
ret = 0;
} else {
ddr_clk_cached = 0;
ret = -1;
}
return ret;
}
@@ -119,7 +128,10 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return (MHZ * scpi_ddr_get_clk_rate());
if (ddr_clk_cached)
return (MHZ * ddr_clk_cached);
else
return (MHZ * scpi_ddr_get_clk_rate());
}
static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,