From 3e6cf0d71a43636cf391ce3e084512ca7aaa0695 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Mon, 15 Mar 2021 11:32:31 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: modify SSC config for SATA Signed-off-by: Yifeng Zhao Change-Id: Icdb2079028df1edb8973608ad08a51113e1c9ce8 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 67c3663da80d..08445c1890eb 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -505,7 +505,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) switch (rate) { case 24000000: - if (priv->mode == PHY_TYPE_USB3) { + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ val = readl(priv->mmio + (0x0e << 2)); val &= ~GENMASK(7, 6); @@ -540,7 +540,12 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) writel(0x32, priv->mmio + (0x11 << 2)); writel(0xf0, priv->mmio + (0xa << 2)); - + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(7, 4); + val |= 0x50; + writel(val, priv->mmio + (0x1f << 2)); } break; default: