From 3ef4c2204f9be3f0877333b5d35ab11e322ed90d Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Mon, 8 Oct 2018 17:18:55 +0800 Subject: [PATCH] drm/rockchip: dsi: Bypass TLP clock lane and data lanes counter threshold Most of TLP is contributed by the counter programming: TLP = ((counter_threshold + 1) x TXBYTECLKHS) + constant_time where: constant_time corresponds to internal D-PHY FSM state and Analog Front End (AFE) timing variation Change-Id: Icee77dee0772afbcecc5e883572061162ed0fc4f Signed-off-by: Wyon Bi --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index b458c844450f..5639a7ce3b2d 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -650,8 +650,8 @@ static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} }; - u8 hsfreqrange; - unsigned int index; + u8 hsfreqrange, counter; + unsigned int index, txbyteclkhs; for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) @@ -663,6 +663,11 @@ static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) hsfreqrange = hsfreqrange_table[index].hsfreqrange; regmap_write(dphy->regmap, 0x44, HSFREQRANGE(hsfreqrange)); + txbyteclkhs = dsi->lane_mbps >> 3; + counter = txbyteclkhs * 60 / NSEC_PER_USEC; + regmap_write(dphy->regmap, 0x60, 0x80 | counter); + regmap_write(dphy->regmap, 0x70, 0x80 | counter); + if (IS_DSI0(dsi)) dw_mipi_dsi_phy_pll_init(dsi); }