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arm64: dts: rockchip: Add usb2 phy nodes for RK3568 Soc

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Change-Id: I20f7520d02972c853f4de2c526072e94d8343ec9
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2020-10-22 10:55:16 +08:00
committed by Tao Huang
parent 9d2daf8ca1
commit 3fefaf4ac8
1 changed files with 52 additions and 0 deletions
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52
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -258,6 +258,16 @@
reg = <0x0 0xfdc90000 0x0 0x1000>;
};
usb2phy0_grf: syscon@fdca0000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca0000 0x0 0x8000>;
};
usb2phy1_grf: syscon@fdca8000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca8000 0x0 0x8000>;
};
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -1317,6 +1327,48 @@
status = "disabled";
};
usb2phy0: usb2-phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USBPHY0_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy";
rockchip,usbgrf = <&usb2phy0_grf>;
status = "disabled";
u2phy0_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
usb2phy1: usb2-phy@fe8b0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8b0000 0x0 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USBPHY1_REF>;
clock-names = "phyclk";
rockchip,usbgrf = <&usb2phy1_grf>;
status = "disabled";
u2phy1_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
u2phy1_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;