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UPSTREAM: KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set

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According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.

Fixes: c01d6a1802 ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com
(cherry picked from commit 2a71fabf6a)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I47d26a718844563278a5f820452d85a773452f58
This commit is contained in:
Alexandru Elisei
2021-06-18 11:51:39 +01:00
committed by Will Deacon
parent ab687fde9a
commit 4010ce1626
1 changed files with 1 additions and 0 deletions
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arch/arm64/kvm/pmu-emul.c
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@@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
if (val & ARMV8_PMU_PMCR_P) {
mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
for_each_set_bit(i, &mask, 32)
kvm_pmu_set_counter_value(vcpu, i, 0);
}