From 4124fe99362fa9751541a7e52ecf5295fa1bc7c7 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 20 Oct 2017 11:08:30 +0800 Subject: [PATCH] clk: rockchip: rk3128: fix up the hclk_vio clk description set hclk_vio_niu as critical clock. Change-Id: Ib9e182ac93038df34eadae502fc18df5c0854ef9 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3128.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 23ddfc9a2b2a..1b53b0f95043 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -274,8 +274,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0, RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), - COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0, - RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, + FACTOR_GATE(HCLK_VIO, "hclk_vio", "aclk_vio0", 0, 1, 4, RK2928_CLKGATE_CON(0), 11, GFLAGS), /* PD_PERI */ @@ -317,7 +316,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(10), 1, GFLAGS), GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), - GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED, + GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", 0, RK2928_CLKGATE_CON(2), 15, GFLAGS), COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, @@ -576,6 +575,7 @@ static const char *const rk3128_critical_clocks[] __initconst = { "pclk_peri", "pclk_pmu", "sclk_timer5", + "hclk_vio_niu", }; static void __iomem *rk312x_reg_base;