From 41cd4eff81215e331f569ccd5101eefa716e073f Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Wed, 28 Nov 2018 09:36:58 +0800 Subject: [PATCH] lcd: update pll setting for tl1 tcon_pll performance [1/1] PD#172587 Problem: tcon pll performance is not good when frac enabled with old setting Solution: update tcon pll setting Verify: x301 Change-Id: Ib5deb5c643afa243876c0e4703f835e503fffc2e Signed-off-by: Evoke Zhang --- drivers/amlogic/media/vout/lcd/lcd_clk_config.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c index 295059c010ec..33a3e28d9385 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c @@ -517,6 +517,8 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { case LCD_LVDS: + lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x000704ad); + mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200704ad); mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300704ad); @@ -525,7 +527,8 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108); mdelay(10); - lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30); + //lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30); + lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10051400); mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0); mdelay(10); @@ -541,6 +544,8 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) mdelay(10); break; case LCD_VBYONE: + lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x000f04f7); + mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200f04f7); mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300f04f7); @@ -563,6 +568,8 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) mdelay(10); break; case LCD_P2P: + lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x000f04e1); + mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200604e1); mdelay(10); lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300604e1);