From 41fe643f8cdc438aaccf7b0005c23c2b3e6d02e8 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Sat, 12 Mar 2022 11:55:15 +0800 Subject: [PATCH] drm/rockchp: dw-dp: enable video stream fifo overflow irq Signed-off-by: Zhang Yubing Change-Id: I73e33d60db8886b150c390b387ba360bafbc0b72 --- drivers/gpu/drm/rockchip/dw-dp.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 94fc6a4987d4..a7400bf99953 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -171,6 +171,9 @@ #define DPTX_AUX_DATA3 0x0b14 #define DPTX_GENERAL_INTERRUPT 0x0d00 +#define VIDEO_FIFO_OVERFLOW_STREAM3 BIT(26) +#define VIDEO_FIFO_OVERFLOW_STREAM2 BIT(20) +#define VIDEO_FIFO_OVERFLOW_STREAM1 BIT(14) #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) #define SDP_EVENT_STREAM0 BIT(4) @@ -2900,6 +2903,14 @@ static void dw_dp_init(struct dw_dp *dp) dw_dp_hpd_init(dp); dw_dp_aux_init(dp); + + regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, + VIDEO_FIFO_OVERFLOW_STREAM0 | VIDEO_FIFO_OVERFLOW_STREAM1 | + VIDEO_FIFO_OVERFLOW_STREAM2 | VIDEO_FIFO_OVERFLOW_STREAM3, + FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM0, 1) | + FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM1, 1) | + FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM2, 1) | + FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM3, 1)); } static void dw_dp_encoder_enable(struct drm_encoder *encoder) @@ -5084,6 +5095,30 @@ static irqreturn_t dw_dp_irq_handler(int irq, void *data) if (value & HDCP_EVENT) dw_dp_handle_hdcp_event(dp); + if (value & VIDEO_FIFO_OVERFLOW_STREAM0) { + dev_err_ratelimited(dp->dev, "video fifo overflow stream0\n"); + regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, + VIDEO_FIFO_OVERFLOW_STREAM0); + } + + if (value & VIDEO_FIFO_OVERFLOW_STREAM1) { + dev_err_ratelimited(dp->dev, "video fifo overflow stream1\n"); + regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, + VIDEO_FIFO_OVERFLOW_STREAM1); + } + + if (value & VIDEO_FIFO_OVERFLOW_STREAM2) { + dev_err_ratelimited(dp->dev, "video fifo overflow stream2\n"); + regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, + VIDEO_FIFO_OVERFLOW_STREAM2); + } + + if (value & VIDEO_FIFO_OVERFLOW_STREAM3) { + dev_err_ratelimited(dp->dev, "video fifo overflow stream3\n"); + regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, + VIDEO_FIFO_OVERFLOW_STREAM3); + } + return IRQ_HANDLED; }