From 422fcf506834a99552df9b4a9fd3fac429b459f0 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 19 Feb 2025 16:12:45 +0800 Subject: [PATCH] soc: rockchip: cpuinfo: Add support to parse 'cpu-code1' Change-Id: I080efaae76c28fd255c314fc9033efcc02457d4d Signed-off-by: Finley Xiao --- drivers/soc/rockchip/rockchip-cpuinfo.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/soc/rockchip/rockchip-cpuinfo.c b/drivers/soc/rockchip/rockchip-cpuinfo.c index ec1921b0d2ef..c37a0aa43a3c 100644 --- a/drivers/soc/rockchip/rockchip-cpuinfo.c +++ b/drivers/soc/rockchip/rockchip-cpuinfo.c @@ -29,20 +29,34 @@ static int rockchip_cpuinfo_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct nvmem_cell *cell; unsigned char *efuse_buf, buf[16]; + bool is_cpu_code1_valid = false; size_t len = 0; int i; - cell = nvmem_cell_get(dev, "cpu-code"); + cell = nvmem_cell_get(dev, "cpu-code1"); if (!IS_ERR(cell)) { efuse_buf = nvmem_cell_read(cell, &len); nvmem_cell_put(cell); if (IS_ERR(efuse_buf)) return PTR_ERR(efuse_buf); - - if (len == 2) + if (len == 2 && efuse_buf[0] && efuse_buf[1]) { rockchip_set_cpu((efuse_buf[0] << 8 | efuse_buf[1])); + is_cpu_code1_valid = true; + } kfree(efuse_buf); } + if (!is_cpu_code1_valid) { + cell = nvmem_cell_get(dev, "cpu-code"); + if (!IS_ERR(cell)) { + efuse_buf = nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + if (IS_ERR(efuse_buf)) + return PTR_ERR(efuse_buf); + if (len == 2) + rockchip_set_cpu((efuse_buf[0] << 8 | efuse_buf[1])); + kfree(efuse_buf); + } + } cell = nvmem_cell_get(dev, "cpu-version"); if (!IS_ERR(cell)) {