diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 316bf6054fa1..21da1fb3618e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -842,6 +842,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb \ + rv1109-38-v10-spi-nand.dtb \ rv1109-evb-ddr3-v10.dtb \ rv1109-evb-ddr3-v12.dtb \ rv1109-evb-lp3-v10.dtb \ diff --git a/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts b/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts new file mode 100644 index 000000000000..fe15fa968494 --- /dev/null +++ b/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1109.dtsi" +#include "rv11xx-ipc.dtsi" + +/ { + model = "Rockchip RV1109 38 V10 SPI NAND DDR3 Board"; + compatible = "rockchip,rv1109-38-v10-spi-nand", "rockchip,rv1109"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs snd_aloop.index=7"; + }; + + /delete-node/ vdd-npu; + /delete-node/ vdd-vepu; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_dvdd: vcc-dvdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_dvdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vcc3v3_sys: vcc33sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-init-microvolt = <825000>; + regulator-always-on; + regulator-boot-on; + pwm-supply = <&vcc3v3_sys>; + status = "okay"; + }; + + /* + * pwm1 is reserved as voltage adjustment in hardware + * use fixed regulator to avoid voltage adjustment by software + */ + vdd_logic_npu_vepu: vdd-logic-npu-vepu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic_npu_vepu"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <880000>; + regulator-init-microvolt = <825000>; + regulator-always-on; + regulator-boot-on; + pwm-supply = <&vcc3v3_sys>; + status = "okay"; + }; + + vdd_logic_npu_vepu_fixed: vdd-logic-npu-vepu-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_logic_npu_vepu-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <825000>; + }; +}; + +&csi_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_in>; + }; + }; + }; +}; + +&gmac { + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; + assigned-clock-rates = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level0_pins>; + + phy-handle = <&phy>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + os04a10: os04a10@36 { + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_MIPICSI_OUT>; + clock-names = "xvclk"; + power-domains = <&power RV1126_PD_VI>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&mipicsi_clk0>; + avdd-supply = <&vcc3v3_sys>; + dovdd-supply = <&vcc_1v8>; + dvdd-supply = <&vcc_dvdd>; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mdio { + phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&nandc { + status = "okay"; +}; + +&npu { + npu-supply = <&vdd_logic_npu_vepu_fixed>; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio0-supply = <&vcc3v3_sys>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vcc3v3_sys>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc3v3_sys>; + vccio6-supply = <&vcc3v3_sys>; + vccio7-supply = <&vcc3v3_sys>; +}; + +&rkisp { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + isp_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + isp_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&ispp_in>; + }; + }; + }; +}; + +&rkispp { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ispp_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_out>; + }; + }; +}; + +&rkvenc { + venc-supply = <&vdd_logic_npu_vepu_fixed>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + ) + >; +}; + +&sfc { + status = "okay"; +};