From 42e759004f12ff299e15a04597276494bee16237 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 4 Mar 2024 19:53:21 +0800 Subject: [PATCH] pwm: rockchip: add one period delay before disabling the dclk For pwm v4, the disable operation, which sets polarity to inactive state, will not take effect until the end of current period. Change-Id: Ie632b69d06495d96b79b9c743e69175cd5c175ed Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index d759bf5d0264..78ce756b997f 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -783,6 +783,8 @@ static void rockchip_pwm_config_v4(struct pwm_chip *chip, struct pwm_device *pwm static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm, bool enable) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + struct pwm_state curstate; + unsigned long delay_us; int ret; if (enable) { @@ -793,8 +795,12 @@ static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm, writel_relaxed(PWM_EN(enable) | PWM_CLK_EN(enable), pc->base + ENABLE); - if (!enable) + if (!enable) { + pwm_get_state(pwm, &curstate); + delay_us = DIV_ROUND_UP_ULL(curstate.period, NSEC_PER_USEC); + fsleep(delay_us); clk_disable(pc->clk); + } return 0; }