diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index c275078cfbca..f102800b7780 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -33,6 +33,10 @@ }; }; +&dmc { + wait-mode = ; +}; + &ebc { status = "okay"; }; diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 866834f3ecd2..0d15c1f4a9a1 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -5168,7 +5168,7 @@ static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) props.max_brightness = 255; panel->base.backlight = - devm_backlight_device_register(dev, "dcs-backlight", + devm_backlight_device_register(dev, dev_name(dev), dev, panel, &dcs_bl_ops, &props); if (IS_ERR(panel->base.backlight)) { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 50d87c3abe8f..d3628f938892 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5295,23 +5295,31 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_st if (!vpstate->afbc_en && (fb->format->format == DRM_FORMAT_XRGB2101010 || fb->format->format == DRM_FORMAT_XBGR2101010)) { - DRM_ERROR("RK3588 unsupported linear XRGB2101010 at %s\n", win->name); + DRM_ERROR("Unsupported linear XRGB2101010 at %s\n", win->name); + return -EINVAL; + } + + if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv) { + DRM_ERROR("Unsupported linear yuv format at %s\n", win->name); return -EINVAL; } } - if (vp->vop2->version > VOP_VERSION_RK3568) { - if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv && !is_vop3(vop2)) { - DRM_ERROR("Unsupported linear yuv format at %s\n", win->name); - return -EINVAL; - } + /* Cluster can't support xmirror/rotate90/rotate270 when it isn't fbc format. */ + if (vop2_cluster_window(win) && !vpstate->afbc_en && + (pstate->rotation & (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270))) { + DRM_ERROR("Unsupported linear rotation(%d) format at %s\n", + pstate->rotation, win->name); + return -EINVAL; + } - if (vop2_cluster_window(win) && !vpstate->afbc_en && - (win->supported_rotations & pstate->rotation)) { - DRM_ERROR("Unsupported linear rotation(%d) format at %s\n", - pstate->rotation, win->name); - return -EINVAL; - } + /* Cluster can't support xmirror/ymirror/rotate90/rotate270 when it is tiled format. */ + if (vop2_cluster_window(win) && vpstate->tiled_en && + (pstate->rotation & (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | + DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270))) { + DRM_ERROR("Unsupported x/y mirror or rotation(%d) tiled format at %s\n", + pstate->rotation, win->name); + return -EINVAL; } if (win->feature & WIN_FEATURE_CLUSTER_SUB) { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index a8dda26f6bea..949df47cd342 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -2861,6 +2861,7 @@ static const struct vop2_win_regs rk3528_cluster0_win_data = { .y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8), .r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9), .csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x7, 10), + .ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 21), .axi_yrgb_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 0), .axi_uv_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 5), }; @@ -2883,6 +2884,7 @@ static const struct vop2_win_regs rk3568_cluster0_win_data = { .y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8), .r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9), .csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10), + .ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 21), .axi_yrgb_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 0), .axi_uv_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 5), .axi_id = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 13), @@ -2906,6 +2908,7 @@ static const struct vop2_win_regs rk3568_cluster1_win_data = { .y2r_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 8), .r2y_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 9), .csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x3, 10), + .ymirror = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 21), .axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0), .axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5), .axi_id = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 13), @@ -3560,6 +3563,7 @@ static const struct vop2_win_regs rk3576_cluster0_win_data = { .csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x7, 10), .axi_yrgb_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 0), .axi_uv_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 5), + .ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 21), .csc_y2r_path_sel = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 24), }; @@ -3611,6 +3615,7 @@ static const struct vop2_win_regs rk3576_cluster1_win_data = { .csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x7, 10), .axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0), .axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5), + .ymirror = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 21), .csc_y2r_path_sel = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 24), }; diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c index 95d3a06711ab..846ea3fbabcc 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c @@ -10055,10 +10055,9 @@ dhd_bus_start(dhd_pub_t *dhdp) } #ifdef BCMPCIE -#if defined(CUSTOMER_HW_ROCKCHIP) - if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)) - rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE); -#endif /* CUSTOMER_HW_ROCKCHIP && BCMPCIE */ +#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION) + rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE); +#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */ #endif /* BCMPCIE */ #if defined(BCMPCIE) diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie.c index c0a4d770cc83..001b892abbd7 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie.c @@ -72,6 +72,9 @@ #include #include +#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION) +#include +#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */ #ifdef BCM_ROUTER_DHD #include #define STR_END "END\0\0" @@ -7615,6 +7618,13 @@ dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag) dhdpcie_bus_intr_disable(bus); dhdpcie_free_irq(bus); } +#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION) + if (!rk_dhd_bus_pcie_wait_for_l1ss(bus)) { + DHD_ERROR(("%s: wait for l1ss success\n", __FUNCTION__)); + } else { + DHD_ERROR(("%s: wait for l1ss failed\n", __FUNCTION__)); + } +#endif dhd_deinit_bus_lp_state_lock(bus); dhd_deinit_bar1_switch_lock(bus); dhd_deinit_backplane_access_lock(bus); diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie_linux.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie_linux.c index 1edae2dc649f..30e8ef9e2b20 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie_linux.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie_linux.c @@ -47,9 +47,9 @@ #include #include #include -#if defined(CUSTOMER_HW_ROCKCHIP) +#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION) #include -#endif /* CUSTOMER_HW_ROCKCHIP */ +#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */ #ifdef CONFIG_ARCH_MSM #if IS_ENABLED(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996) #include @@ -614,17 +614,15 @@ dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus) uint32 rc_l1ss_cap; uint32 ep_l1ss_cap; -#if defined(CUSTOMER_HW_ROCKCHIP) - if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)) { - if (rk_dhd_bus_is_rc_ep_l1ss_capable(bus)) { - DHD_ERROR(("%s L1ss is capable\n", __FUNCTION__)); - return TRUE; - } else { - DHD_ERROR(("%s L1ss is not capable\n", __FUNCTION__)); - return FALSE; - } +#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION) + if (rk_dhd_bus_is_rc_ep_l1ss_capable(bus)) { + DHD_ERROR(("%s L1ss is capable\n", __FUNCTION__)); + return TRUE; + } else { + DHD_ERROR(("%s L1ss is not capable\n", __FUNCTION__)); + return FALSE; } -#endif /* CUSTOMER_HW_ROCKCHIP */ +#endif /* RC Extendend Capacility */ rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS, diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/rk_dhd_pcie_linux.h b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/rk_dhd_pcie_linux.h index 80501a3cfd41..10960986ad1e 100644 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/rk_dhd_pcie_linux.h +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/rk_dhd_pcie_linux.h @@ -24,7 +24,7 @@ rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable) } /* Disable ASPM of RC and EP */ - printf("%s: %s L1ss\n", __FUNCTION__, enable?"enable":"disable"); + pr_err("%s: %s L1ss\n", __FUNCTION__, enable ? "enable" : "disable"); pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable); } @@ -34,4 +34,27 @@ rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus) return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev); } +static inline int +rk_dhd_bus_pcie_wait_for_l1ss(dhd_bus_t *bus) +{ + u32 val; + int i; + + if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) { + return -1; + } + + pci_read_config_dword(bus->dev, PCIECFGREG_STATUS_CMD, &val); + if (val == (uint32)-1) + return -1; + + for (i = 0; i < 5; i++) { + if (pcie_aspm_ext_is_in_l1sub_state(bus->rc_dev)) + return 0; + msleep(20); + } + + return -1; +} + #endif /* __RK_DHD_PCIE_LINUX_H__ */ diff --git a/drivers/pci/pcie/aspm_ext.c b/drivers/pci/pcie/aspm_ext.c index b8330bce4efb..5160b558313e 100644 --- a/drivers/pci/pcie/aspm_ext.c +++ b/drivers/pci/pcie/aspm_ext.c @@ -11,6 +11,10 @@ #include #include +#define PCIE_RAS_DES_CAP_SD_STATUS_PM 0xB8 +#define PCIE_RAS_DES_CAP_LISS_SHIFT 13 +#define PCIE_RAS_DES_CAP_LISS_MASK (0x7 << PCIE_RAS_DES_CAP_LISS_SHIFT) +#define PCIE_RAS_DES_CAP_LISS (0x5 << PCIE_RAS_DES_CAP_LISS_SHIFT) static u32 rockchip_pcie_pcie_access_cap(struct pci_dev *pdev, int cap, uint offset, bool is_ext, bool is_write, u32 writeval) @@ -343,4 +347,19 @@ void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bo } EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable); +bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev) +{ + u32 val; + + val = rockchip_pcie_pcie_access_cap(pdev, PCI_EXT_CAP_ID_VNDR, + PCIE_RAS_DES_CAP_SD_STATUS_PM, + true, false, 0); + + if ((val & PCIE_RAS_DES_CAP_LISS_MASK) == PCIE_RAS_DES_CAP_LISS) + return true; + + return false; +} +EXPORT_SYMBOL(pcie_aspm_ext_is_in_l1sub_state); + MODULE_LICENSE("GPL"); diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index df1e155b5c5a..e79a9016525d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -2501,6 +2501,72 @@ rockchip_usb2phy_low_power_enable(struct rockchip_usb2phy *rphy, return ret; } +static int px30_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + int ret; + + if (soc_is_px30s()) { + /* Enable otg port pre-emphasis during non-chirp phase */ + ret = regmap_update_bits(rphy->grf, 0x8000, GENMASK(2, 0), BIT(2)); + if (ret) + return ret; + + /* Set otg port squelch trigger point configure to 100mv */ + ret = regmap_update_bits(rphy->grf, 0x8004, GENMASK(7, 5), 0x40); + if (ret) + return ret; + + ret = regmap_update_bits(rphy->grf, 0x8008, BIT(0), 0x1); + if (ret) + return ret; + + /* Turn off otg port differential receiver in suspend mode */ + ret = regmap_update_bits(rphy->grf, 0x8030, BIT(2), 0); + if (ret) + return ret; + + /* Enable host port pre-emphasis during non-chirp phase */ + ret = regmap_update_bits(rphy->grf, 0x8400, GENMASK(2, 0), BIT(2)); + if (ret) + return ret; + + /* Set host port squelch trigger point configure to 100mv */ + ret = regmap_update_bits(rphy->grf, 0x8404, GENMASK(7, 5), 0x40); + if (ret) + return ret; + + ret = regmap_update_bits(rphy->grf, 0x8408, BIT(0), 0x1); + if (ret) + return ret; + + /* Turn off host port differential receiver in suspend mode */ + ret = regmap_update_bits(rphy->grf, 0x8430, BIT(2), 0); + if (ret) + return ret; + } else { + /* Open debug mode for tuning */ + ret = regmap_write(rphy->grf, 0x2c, 0xffff0400); + if (ret) + return ret; + + /* Open pre-emphasize in non-chirp state for otg port */ + ret = regmap_write(rphy->grf, 0x0, 0x00070004); + if (ret) + return ret; + + /* Open pre-emphasize in non-chirp state for host port */ + ret = regmap_write(rphy->grf, 0x30, 0x00070004); + if (ret) + return ret; + + /* Turn off differential receiver in suspend mode */ + ret = regmap_write(rphy->grf, 0x18, 0x00040000); + if (ret) + return ret; + } + return 0; +} + static int rk312x_usb2phy_tuning(struct rockchip_usb2phy *rphy) { int ret; @@ -2585,65 +2651,26 @@ static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) { int ret; - if (soc_is_px30s()) { - /* Enable otg port pre-emphasis during non-chirp phase */ - ret = regmap_update_bits(rphy->grf, 0x8000, GENMASK(2, 0), BIT(2)); - if (ret) - return ret; + /* Open debug mode for tuning */ + ret = regmap_write(rphy->grf, 0x2c, 0xffff0400); + if (ret) + return ret; - /* Set otg port squelch trigger point configure to 100mv */ - ret = regmap_update_bits(rphy->grf, 0x8004, GENMASK(7, 5), 0x40); - if (ret) - return ret; + /* Open pre-emphasize in non-chirp state for otg port */ + ret = regmap_write(rphy->grf, 0x0, 0x00070004); + if (ret) + return ret; - ret = regmap_update_bits(rphy->grf, 0x8008, BIT(0), 0x1); - if (ret) - return ret; + /* Open pre-emphasize in non-chirp state for host port */ + ret = regmap_write(rphy->grf, 0x30, 0x00070004); + if (ret) + return ret; - /* Turn off otg port differential reciver in suspend mode */ - ret = regmap_update_bits(rphy->grf, 0x8030, BIT(2), 0); - if (ret) - return ret; + /* Turn off differential receiver in suspend mode */ + ret = regmap_write(rphy->grf, 0x18, 0x00040000); + if (ret) + return ret; - /* Enable host port pre-emphasis during non-chirp phase */ - ret = regmap_update_bits(rphy->grf, 0x8400, GENMASK(2, 0), BIT(2)); - if (ret) - return ret; - - /* Set host port squelch trigger point configure to 100mv */ - ret = regmap_update_bits(rphy->grf, 0x8404, GENMASK(7, 5), 0x40); - if (ret) - return ret; - - ret = regmap_update_bits(rphy->grf, 0x8408, BIT(0), 0x1); - if (ret) - return ret; - - /* Turn off host port differential reciver in suspend mode */ - ret = regmap_update_bits(rphy->grf, 0x8430, BIT(2), 0); - if (ret) - return ret; - } else { - /* Open debug mode for tuning */ - ret = regmap_write(rphy->grf, 0x2c, 0xffff0400); - if (ret) - return ret; - - /* Open pre-emphasize in non-chirp state for otg port */ - ret = regmap_write(rphy->grf, 0x0, 0x00070004); - if (ret) - return ret; - - /* Open pre-emphasize in non-chirp state for host port */ - ret = regmap_write(rphy->grf, 0x30, 0x00070004); - if (ret) - return ret; - - /* Turn off differential receiver in suspend mode */ - ret = regmap_write(rphy->grf, 0x18, 0x00040000); - if (ret) - return ret; - } return 0; } @@ -3240,6 +3267,63 @@ static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = { #define ROCKCHIP_USB2PHY_DEV_PM NULL #endif /* CONFIG_PM_SLEEP */ +static const struct rockchip_usb2phy_cfg px30_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .phy_tuning = px30_usb2phy_tuning, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .bypass_bc = { 0x0008, 14, 14, 0, 1 }, + .bypass_otg = { 0x0018, 15, 15, 1, 0 }, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, + .bypass_host = { 0x048, 15, 15, 1, 0 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .chg_mode = { 0x0100, 8, 0, 0, 0x1d7 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { { .reg = 0x100, @@ -4261,7 +4345,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { static const struct of_device_id rockchip_usb2phy_dt_match[] = { #ifdef CONFIG_CPU_PX30 - { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,px30-usb2phy", .data = &px30_phy_cfgs }, #endif #ifdef CONFIG_CPU_RK1808 { .compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs }, diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h index 6a0d198a2e6e..9ab019e31430 100644 --- a/include/dt-bindings/soc/rockchip-system-status.h +++ b/include/dt-bindings/soc/rockchip-system-status.h @@ -55,5 +55,6 @@ #define DMC_WAIT_MODE_VOP_LINE (0x1 << 2) #define DMC_WAIT_MODE_VOP_AUTO (0x1 << 3) #define DMC_WAIT_MODE_ISP_VBANK (0x1 << 4) +#define DMC_WAIT_MODE_EBC_VBANK (0x1 << 5) #endif diff --git a/include/linux/aspm_ext.h b/include/linux/aspm_ext.h index 1bd141e56a45..b253cc4a29ca 100644 --- a/include/linux/aspm_ext.h +++ b/include/linux/aspm_ext.h @@ -8,9 +8,11 @@ #if IS_REACHABLE(CONFIG_PCIEASPM_EXT) bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent); void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable); +bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev); #else static inline bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent) { return false; } static inline void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable) {} +static inline bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev) { return false; } #endif #endif