diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c index ecf95776696b..ca64588a2bf0 100644 --- a/drivers/clk/rockchip/clk-rk1808.c +++ b/drivers/clk/rockchip/clk-rk1808.c @@ -12,8 +12,10 @@ #define RK1808_GRF_SOC_STATUS0 0x480 #define RK1808_UART_FRAC_MAX_PRATE 800000000 -#define RK1808_PDM_FRAC_MAX_PRATE 800000000 -#define RK1808_I2S_FRAC_MAX_PRATE 800000000 +#define RK1808_PDM_FRAC_MAX_PRATE 300000000 +#define RK1808_I2S_FRAC_MAX_PRATE 600000000 +#define RK1808_VOP_RAW_FRAC_MAX_PRATE 300000000 +#define RK1808_VOP_LITE_FRAC_MAX_PRATE 400000000 enum rk1808_plls { apll, dpll, cpll, gpll, npll, ppll, @@ -479,7 +481,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "dclk_vopraw_frac", "dclk_vopraw_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(6), 0, RK1808_CLKGATE_CON(3), 2, GFLAGS, - &rk1808_dclk_vopraw_fracmux, 0), + &rk1808_dclk_vopraw_fracmux, RK1808_VOP_RAW_FRAC_MAX_PRATE), GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0, RK1808_CLKGATE_CON(3), 3, GFLAGS), @@ -489,7 +491,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "dclk_voplite_frac", "dclk_voplite_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(8), 0, RK1808_CLKGATE_CON(3), 5, GFLAGS, - &rk1808_dclk_voplite_fracmux, 0), + &rk1808_dclk_voplite_fracmux, RK1808_VOP_LITE_FRAC_MAX_PRATE), GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0, RK1808_CLKGATE_CON(3), 6, GFLAGS), @@ -816,7 +818,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(40), 0, RK1808_CLKGATE_CON(11), 10, GFLAGS, - &rk1808_uart1_fracmux, 0), + &rk1808_uart1_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0, RK1808_CLKGATE_CON(11), 11, GFLAGS), @@ -829,7 +831,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(43), 0, RK1808_CLKGATE_CON(11), 14, GFLAGS, - &rk1808_uart2_fracmux, 0), + &rk1808_uart2_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0, RK1808_CLKGATE_CON(11), 15, GFLAGS), @@ -842,7 +844,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(46), 0, RK1808_CLKGATE_CON(12), 2, GFLAGS, - &rk1808_uart3_fracmux, 0), + &rk1808_uart3_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0, RK1808_CLKGATE_CON(12), 3, GFLAGS), @@ -855,7 +857,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(49), 0, RK1808_CLKGATE_CON(12), 6, GFLAGS, - &rk1808_uart4_fracmux, 0), + &rk1808_uart4_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0, RK1808_CLKGATE_CON(12), 7, GFLAGS), @@ -868,7 +870,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(52), 0, RK1808_CLKGATE_CON(12), 10, GFLAGS, - &rk1808_uart5_fracmux, 0), + &rk1808_uart5_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0, RK1808_CLKGATE_CON(12), 11, GFLAGS), @@ -881,7 +883,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(55), 0, RK1808_CLKGATE_CON(12), 14, GFLAGS, - &rk1808_uart6_fracmux, 0), + &rk1808_uart6_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0, RK1808_CLKGATE_CON(12), 15, GFLAGS), @@ -894,7 +896,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(58), 0, RK1808_CLKGATE_CON(13), 2, GFLAGS, - &rk1808_uart7_fracmux, 0), + &rk1808_uart7_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0, RK1808_CLKGATE_CON(13), 3, GFLAGS), @@ -1007,7 +1009,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(33), 0, RK1808_CLKGATE_CON(17), 13, GFLAGS, - &rk1808_i2s0_8ch_tx_fracmux, 0), + &rk1808_i2s0_8ch_tx_fracmux, RK1808_I2S_FRAC_MAX_PRATE), COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(32), 12, 1, MFLAGS, RK1808_CLKGATE_CON(17), 14, GFLAGS), @@ -1021,7 +1023,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(35), 0, RK1808_CLKGATE_CON(18), 1, GFLAGS, - &rk1808_i2s0_8ch_rx_fracmux, 0), + &rk1808_i2s0_8ch_rx_fracmux, RK1808_I2S_FRAC_MAX_PRATE), COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(34), 12, 1, MFLAGS, RK1808_CLKGATE_CON(18), 2, GFLAGS), @@ -1089,7 +1091,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, RK1808_PMU_CLKSEL_CON(5), 0, RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS, - &rk1808_uart0_pmu_fracmux, 0), + &rk1808_uart0_pmu_fracmux, RK1808_UART_FRAC_MAX_PRATE), GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, RK1808_PMU_CLKGATE_CON(1), 3, GFLAGS),