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arm64: dts: rockchip: px30s: add scmi/opp-table/dmc_fsp node

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Change-Id: Ic1b24c9dec7746f1d1ea1e499de64fcb37e55802
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Elaine Zhang
2021-10-09 11:17:59 +08:00
committed by Tao Huang
parent d9b0208167
commit 43da524240
3 changed files with 527 additions and 1 deletions
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141
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -16,6 +16,7 @@
#include <dt-bindings/suspend/rockchip-px30.h>
#include <dt-bindings/thermal/thermal.h>
#include "px30-dram-default-timing.dtsi"
#include "px30s-dram-default-timing.dtsi"
/ {
compatible = "rockchip,px30";
@@ -230,6 +231,58 @@
};
};
px30s_cpu0_opp_table: px30s-cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <900000 900000 1150000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <975000 975000 1150000>;
clock-latency-ns = <40000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-microvolt = <1000000 1000000 1150000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1025000 1025000 1150000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1075000 1075000 1150000>;
clock-latency-ns = <40000>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1150000 1150000 1150000>;
clock-latency-ns = <40000>;
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
@@ -279,6 +332,24 @@
compatible = "linaro,optee-tz";
method = "smc";
};
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0x82000010>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
sdei: sdei {
compatible = "arm,sdei-1.0";
method = "smc";
};
};
gmac_clkin: external-gmac-clock {
@@ -337,6 +408,11 @@
clock-output-names = "xin32k";
};
scmi_shmem: scmi-shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x0010f000 0x0 0x100>;
};
pmu: power-management@ff000000 {
compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x1000>;
@@ -1388,6 +1464,27 @@
};
};
px30s_gpu_opp_table: px30s-gpu-opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
};
opp-520000000 {
opp-hz = /bits/ 64 <520000000>;
opp-microvolt = <1000000>;
};
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <1>;
@@ -1841,7 +1938,7 @@
SYS_STATUS_VIDEO_1080P 450000
SYS_STATUS_BOOST 528000
SYS_STATUS_ISP 666000
SYS_STATUS_PERFORMANCE 666000
SYS_STATUS_PERFORMANCE 1056000
>;
auto-min-freq = <328000>;
auto-freq-en = <1>;
@@ -1857,6 +1954,20 @@
};
};
dmc_fsp: dmc-fsp {
compatible = "rockchip,px30s-dmc-fsp";
debug_print_level = <0>;
phy_de_skew_en = <1>;
ddr3_params = <&ddr3_params>;
ddr4_params = <&ddr4_params>;
lpddr2_params = <&lpddr2_params>;
lpddr3_params = <&lpddr3_params>;
lpddr4_params = <&lpddr4_params>;
ddr_timing = <&ddr_timing>;
status = "okay";
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
@@ -1922,6 +2033,34 @@
};
};
px30s_dmc_opp_table: px30s-dmc-opp-table {
compatible = "operating-points-v2";
opp-328000000 {
opp-hz = /bits/ 64 <328000000>;
opp-microvolt = <1000000>;
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <1000000>;
};
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1000000>;
};
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-microvolt = <1000000>;
status = "disabled";
};
/* 1056M only for LP4 */
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <1000000>;
status = "disabled";
};
};
dmcdbg: dmcdbg {
compatible = "rockchip,px30-dmcdbg";
status = "okay";

379
arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,379 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/px30-dram.h>
/ {
ddr3_params: ddr3-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <300>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <120>;
phy_odt = <133>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <333>;
phy_odt_en_freq = <333>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xf>;
phy_ca_sr_odten = <0x3>;
phy_clk_sr_odten = <0x3>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xf>;
phy_ca_sr_odtoff = <0x3>;
phy_clk_sr_odtoff = <0x3>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <DDR3_DEFAULT>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
ddr4_params: ddr4-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <500>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <120>;
phy_odt = <121>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <500>;
phy_odt_en_freq = <500>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xe>;
phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xe>;
phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <DDR4_DEFAULT>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <(((3 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | \
((2 << 0 | 0 << 2 | 2 << 4 | 1 << 6) << 8) | \
((3 << 0 | 2 << 2 | 1 << 4 | 2 << 6) << 16) | \
((3 << 0 | 0 << 2 | 1 << 4 | 0 << 6) << 24))>;
dq_map_cs0_dq_h = <(((2 << 0 | 0 << 2 | 0 << 4 | 1 << 6) << 0) | \
((3 << 0 | 3 << 2 | 2 << 4 | 1 << 6) << 8) | \
((1 << 0 | 3 << 2 | 2 << 4 | 0 << 6) << 16) | \
((3 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 24))>;
dq_map_cs1_dq_l = <(((2 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 0) | \
((3 << 0 | 1 << 2 | 3 << 4 | 0 << 6) << 8) | \
((2 << 0 | 3 << 2 | 0 << 4 | 3 << 6) << 16) | \
((2 << 0 | 1 << 2 | 0 << 4 | 1 << 6) << 24))>;
dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 1 << 4 | 0 << 6) << 0) | \
((2 << 0 | 2 << 2 | 3 << 4 | 0 << 6) << 8) | \
((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 16) | \
((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 24))>;
};
lpddr2_params: lpddr2-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <528>;
freq_1 = <328>;
freq_2 = <450>;
freq_3 = <528>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <0>;
phy_odt = <0>;
phy_odt_puup_en = <0>;
phy_odt_pudn_en = <0>;
/* odt enable freq */
dram_dq_odt_en_freq = <625>;
phy_odt_en_freq = <625>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xe>;
phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xe>;
phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
lpddr3_params: lpddr3-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <786>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <240>;
phy_odt = <121>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <333>;
phy_odt_en_freq = <333>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0x0>;
phy_ca_sr_odten = <0x0>;
phy_clk_sr_odten = <0x0>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0x0>;
phy_ca_sr_odtoff = <0x0>;
phy_clk_sr_odtoff = <0x0>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
lpddr4_params: lpddr4-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <35>;
phy_ca_drv_odten = <51>;
phy_clk_drv_odten = <47>;
dram_dq_drv_odten = <40>;
/* drv when odt off */
phy_dq_drv_odtoff = <35>;
phy_ca_drv_odtoff = <51>;
phy_clk_drv_odtoff = <47>;
dram_dq_drv_odtoff = <40>;
/* odt info */
dram_odt = <60>;
phy_odt = <80>;
phy_odt_puup_en = <IGNORE_THIS>;
phy_odt_pudn_en = <IGNORE_THIS>;
/* odt enable freq */
dram_dq_odt_en_freq = <800>;
phy_odt_en_freq = <800>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xf>;
phy_ca_sr_odten = <0x0>;
phy_clk_sr_odten = <0x0>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xf>;
phy_ca_sr_odtoff = <0x0>;
phy_clk_sr_odtoff = <0x0>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
/* lp4 odt info */
lp4_ca_odt = <60>;
lp4_drv_pu_cal_odten = <LP4_VDDQ_2_5>;
lp4_drv_pu_cal_odtoff = <LP4_VDDQ_2_5>;
phy_lp4_drv_pulldown_en_odten = <0>;
phy_lp4_drv_pulldown_en_odtoff = <0>;
/* lp4 odt enable freq */
lp4_ca_odt_en_freq = <800>;
/* lp4 cs drv info and ca odt info */
phy_lp4_cs_drv_odten = <0>;
phy_lp4_cs_drv_odtoff = <0>;
lp4_odte_ck_en = <1>;
lp4_odte_cs_en = <1>;
lp4_odtd_ca_en = <0>;
/* lp4 vref info when odt enable */
phy_lp4_dq_vref_odten = <200>;
lp4_dq_vref_odten = <316>;
lp4_ca_vref_odten = <420>; /* CA ODT pins have no action */
/* lp4 vref info when odt disable */
phy_lp4_dq_vref_odtoff = <300>;
lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <420>;
};
};

8
include/dt-bindings/memory/px30-dram.h
View File

@@ -129,4 +129,12 @@
#define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30)
#define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31)
#define LP4_VDDQ_2_5 (0)
#define LP4_VDDQ_3 (1)
#define LP4X_VDDQ_0_6 (0)
#define LP4X_VDDQ_0_5 (1)
#define IGNORE_THIS (0)
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/