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hdmitx: add sspll for hdmi modes

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PD#162511: hdmitx: add sspll for hdmi modes
To reduce EMI issue, enable sspll function under certain modes.

Change-Id: Ib5187aaafbc92eccbdd6a77d1c4828776ff596be
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
This commit is contained in:
Zongdong Jiao
2018-03-19 19:47:20 +08:00
committed by Jianxin Pan
parent 26013145b4
commit 454ecea283
4 changed files with 35 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h
View File

@@ -54,6 +54,8 @@ int read_hpd_gpio_gxl(void);
int hdmitx_ddc_hw_op_gxl(enum ddc_op cmd);
void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk);
void set_hpll_sspll_gxl(enum hdmi_vic vic);
void set_hpll_sspll_g12a(enum hdmi_vic vic);
void set_hpll_od1_gxl(unsigned int div);
void set_hpll_od2_gxl(unsigned int div);
void set_hpll_od3_gxl(unsigned int div);

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1679,7 +1679,7 @@ static void set_phy_by_mode(unsigned int mode)
break;
case 3: /* 1.485Gbps, and below */
default:
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6262);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;

7
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -454,6 +454,9 @@ static void set_hpll_sspll(enum hdmi_vic vic)
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
set_hpll_sspll_g12a(vic);
break;
case MESON_CPU_ID_GXBB:
break;
case MESON_CPU_ID_GXTVBB:
@@ -967,9 +970,7 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev)
next:
hdmitx_set_cts_sys_clk(hdev);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
/* 4K mode doesn't enable SS*/
if ((cd == COLORDEPTH_24B) && (hdev->sspll)
&& (p_enc[j].hpll_clk_out != 5940000))
if ((cd == COLORDEPTH_24B) && (hdev->sspll))
set_hpll_sspll(vic);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);

28
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -350,3 +350,31 @@ int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd)
return ret;
}
void set_hpll_sspll_g12a(enum hdmi_vic vic)
{
switch (vic) {
case HDMI_1920x1080p60_16x9:
case HDMI_1920x1080p50_16x9:
case HDMI_1280x720p60_16x9:
case HDMI_1280x720p50_16x9:
case HDMI_1920x1080i60_16x9:
case HDMI_1920x1080i50_16x9:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1);
/* bit[22:20] hdmi_dpll_fref_sel
* bit[8] hdmi_dpll_ssc_en
* bit[7:4] hdmi_dpll_ssc_dep_sel
*/
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1);
/* 2: 1000ppm 1: 500ppm */
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4);
/* bit[15] hdmi_dpll_sdmnc_en */
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1);
break;
default:
break;
}
}